High throughput supervisory system for ATM switching systems tra

Details High throughput supervisory system for ATM switching systems tra High throughput supervisory system for ATM switching systems tra

1993-02-16

1994-10-25

Hsu, Alpus H.

Multiplex communications

Wide area network

Packet switching

370 942, H04L 1256, H04Q 1104

Patent

active

053596005

ABSTRACT:
In an ATM switching network, ATM (asynchronous transfer mode) self-routing switches are interconnected by facilities carrying STM-N (synchronous transport modules level N) signals. At each inlet of an ATM self-routing switch, an STM overhead is removed from each frame of an incoming STM-N signal to create a vacant interval and the frame is converted according to ATM cell format into a series of data ATM cells, and an idle ATM cell is derived from the vacant interval. A supervisory bit sequence is inserted to the payload field of the idle ATM cell to produce a supervisory ATM cell, and the data and supervisory ATM cells are sent into the ATM switch. At each outlet of the switch, the bit sequence of the supervisory ATM cell is checked to evaluate the quality of the ATM switch and a series of data ATM cells is then converted into an STM-N signal according to STM-N frame format.

REFERENCES:
patent: 5084867 (1992-01-01), Tachibana et al.
patent: 5119369 (1992-06-01), Tanabe et al.
patent: 5144619 (1992-09-01), Munter
patent: 5204857 (1993-04-01), Obara
patent: 5237569 (1993-08-01), Sekihata et al.
patent: 5239544 (1993-08-01), Balzano et al.

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