Chemistry: electrical and wave energy – Apparatus – Electrolytic
Reexamination Certificate
2000-10-30
2002-09-24
Valentine, Donald R. (Department: 1741)
Chemistry: electrical and wave energy
Apparatus
Electrolytic
C204S273000, C204S297010, C204S297060
Reexamination Certificate
active
06454917
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electroplating tool. More particularly, the present invention relates to a copper damascene process of an electroplating tool in a semiconductor.
2. Description of the Related Art
When the integration of the integrated circuit increases, this causes the surface of the chip to have no way of providing ample area for creation of the required internal connections. In order to fulfill the necessary requirements of the metal oxide semiconductor (MOS) transistor after it has been reduced in size, multileveled metal processing is becoming a process used more and more in an integrated circuit device. As the line width of fabrication process decreases, the current density that the metal line withstands is increasingly high. Conventionally, when the metal line is primarily formed of aluminum, the metal line is influenced by the electron migration (EM) effect, and thus lowers the reliability of the device. Moreover, along with the gradual reduction of the metal line, the resistance of the metal line also increases correspondingly. In order to solve the above-described problems encountered by the semiconductor device when it enters deep submicron processing, the minimal use of EM and the low resistance of copper become a consistent choice of semiconductor device manufacturers.
The many advantages of applying copper in the processing of the metal interconnections are such that copper has low resistance, a high melting point, and a high EM resistance. Moreover, the internal line circuit of copper improves the operation rate of the chip. By contrast to aluminum, copper interconnections provide an operation speed twice as high. Since using a metal damascene process to form a copper interconnection structure not only lowers the RC delay rate, but also lowers the electrostatic capacity between the copper interconnections. Therefore, in order to raise the integration and the conduction of the device, copper is the material of choice in the formation of metal interconnection structures.
However, since an etching gas does not easily etch copper, copper conductive wire processing cannot be completed through a conventional processing method. Consequently, a metal damascene process is provided to solve this problem.
In the metal damascene processing, an interconnection is formed by first etching the dielectric layer to form an opening, and then filling the opening with a metal. Since the metal damascene process can fulfill the requirement of having a high reliability and high efficiency during interconnection processing, this process has already become the most preferable choice in a deep submicron interconnection processing.
During the processing of copper interconnections in the related art, through physical vapor deposition (PVD), a thin conformal copper grain layer is formed to cover the openings of the dielectric layer hole. Electroplating is used to form a copper layer, thereafter chemical mechanical polishing (CMP) is used to remove the copper layer that is outside the filled openings and higher than the dielectric layer. Since the quality of copper is rather soft, and the copper layer formed in the related in art is not distributed evenly. Thus, when performing CMP, dishing occurs and causes surface irregularity.
Furthermore, when the copper layer electroplating is performed in the related art, there is only one wafer in each electroplating tool. Hence, manufacturing all of the wafers requires a relatively long period of time. Not only is the manufacturing productivity unable to increase, but also, the production costs increase correspondingly.
SUMMARY OF THE INVENTION
In view of the above, the present invention is to provide an electroplating tool. During electroplating of the copper layer, a batch-type deposition procedure is used to replace the single-wafer-type deposition procedure. Since there are 25 wafers in each batch, thus, the manufacturing productivity increases.
The present invention provides an electroplating tool that includes at least a deposition cassette that is installed in the negative electrode of the electroplating tank, and the copper piece or copper rod is installed in positive electrode of the electroplating room. 25 wafers can be installed in the electroplating room, and each side of the wafer is respectively fixed in place by a wafer clamp. The wafer clamp and negative electrode are connected to each other, and are in electric contact with the wafers. Moreover, the copper rod or copper piece that connects to the positive electrode is a big piece installed on the outside of the opening of the wafer clamp. It can also be made of a comb-like arrangement of 25 copper pieces, respectively interlocked and extending into the gaps between the wafers.
When performing electroplating, the surrounding wafers electrically influence the wafers located in the central portion of the wafer clamp. Thus, the deposition effect is evenly distributed amongst the wafers in the upper portion and on the bottom of the deposition cassette. In order for the deposition effect of each wafer to be uniform, a relatively large voltage is needed to be applied on 1 to 4 wafers located in the upper portion and the lower portion of the deposition cassette. That is, the voltage that is applied on the wafers located in the upper portion and the lower portion of the deposition cassette is 1 to 5 volts greater than the voltage applied on the central wafers.
Moreover, in order to increase the even distribution during copper deposition, the present invention further adds a sound wave vibration apparatus on the bottom and on the two sides of the electroplating tank. Simultaneously, an ultrasonic vibration is provided on the electroplating, thereby causing the copper layer deposited on the wafer to be relatively well distributed.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5264091 (1993-11-01), Lecere et al.
patent: 5458755 (1995-10-01), Fujiyama et al.
J.C.Patents
Taiwan Semiconductor Manufacturing Co. Ltd.
Valentine Donald R.
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