High tensile nitride layer

Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

257412, 257413, H01L 2358, H01L 2976, H01L 2994, H01L 31062

Patent

active

060464941

ABSTRACT:
An insulating layer in a semiconductor device and a process for forming the insulating layer is described. The insulating layer comprises of a nitride layer over the substrate having a residual stress of between -8.times.10.sup.9 dynes/cm.sup.-2 and -3.times.10.sup.10 dynes/cm.sup.-2. The insulating layer can further comprise a doped oxide layer under the nitride layer and can further comprise an interlevel dielectric layer over the nitride layer. Moreover, the nitride layer can be formed by bringing the temperature in a chemical vapor deposition reactor to below 550 degrees Celsius, placing the substrate into the reactor at the temperature, and forming the nitride layer on the substrate. Alternatively, the nitride layer can be formed by pushing the substrate into a chemical vapor deposition reactor at a speed greater than 300 millimeters per minute, and forming the nitride layer on the substrate.

REFERENCES:
patent: 4208780 (1980-06-01), Richman
patent: 4441247 (1984-04-01), Gargini et al.
patent: 4557036 (1985-12-01), Kyuragi et al.
patent: 4650696 (1987-03-01), Raby
patent: 4732801 (1988-03-01), Joshi
patent: 4749631 (1988-06-01), Haluska et al.
patent: 4755480 (1988-07-01), Yau et al.
patent: 4866003 (1989-09-01), Yokoi et al.
patent: 4920073 (1990-04-01), Wei et al.
patent: 4948482 (1990-08-01), Kobayashi et al.
patent: 4966870 (1990-10-01), Barber et al.
patent: 4997518 (1991-03-01), Madokoro
patent: 5089432 (1992-02-01), Yoo
patent: 5180688 (1993-01-01), Bryant et al.
patent: 5275972 (1994-01-01), Ogawa et al.
patent: 5285103 (1994-02-01), Chen et al.
patent: 5314847 (1994-05-01), Watanabe et al.
patent: 5372969 (1994-12-01), Moslehi
patent: 5409858 (1995-04-01), Thakur et al.
patent: 5474955 (1995-12-01), Thakur
R.C. Sun, J.T. Clemens, J.T. Nelson, "Effects of Silicon Nitride Encapsulation on MOS Device Stability". JEEE 18th Annual Proceedings Reliability Physics 1980, pp. 244-251.
A. Hamada, E. Takeda, "AC Hot-Carrier Effect Under Mechanical Stress", IEEE Symposium on VLSI Technology Digest of Technical Papers, Jun. 1992, pp. 98-99.
M. Shimbo, T. Matsuo, "Thermal Stress in CVD PSG and SiO.sub.2 Films on Silicon Substrates", Journal of the electrochemical Society, vol. 130 No. 1 Jan. 1983, pp. 135-138.
K. Okuyama, K. Kubota, T. Hashimoto, S. Ikeda, A. Koike, "Water-Relater Threshold Voltage Instability of Polysilicon TFTs", IEDM International Electron Devices Meeting, Dec. 1993, pp. 527-530.
N. Lifshitz, G. Smolinsky, "Water-Related Charge Motion in Dielectrics", Journal of the Electrochemical Society, vol. 136, No. 8, Aug. 1989, pp. 2335-2340.
M. Noyori, et al, "Comparisons of Instabilities in Scaled CMOS Devices Between Plastic and Hermetically Encapsulated Devices", IEEE Transactions on Reliability, Aug. 1983, pp. 323-329.
Wolf, Silicon Processing for the VLSI Era, vol. 1: Process Tech. pp. 191-195, 1986.
W. H. Stinebaugh, Jr., A. Harrus, W.R. Knolle, "Correlation of Gm Degradation of Submicrometer MOSFET's with Refractive Index and Mechanical Stress of Encapsulation Materials", IEEE Transactions on Electron Devices, Vo. 36, No. 3, Mar. 1989, pp. 542-547.
C.E. Blat, E.H. Nicollian, E.H. Poindexter, "Mechanism of Negative-Blas-Temperature Instability", Journal of Applied Physics, vol. 69, No.3, Feb. 1991, pp. 1712-1720.
J. Takahashi, K. Machida, N. Shimoyama, K. Minegishi, "Water Trapping effect of Point Defects in Interlayer Plasma CVD SiO2 Films", Proceedings Ninth International VLSI Multilevel Interconnection Converence (VMIC), Jun. 1992, pp. 331-336.
N. Stojadinovic, S. Dimitrijev, "Instabilities in MOS Transistors", Microelectroncs and Relibility, 1989, vol. 29, No.3 pp. 371-380.
K. Shmokawa, T. Usami, S. Tokitou, N. Hirashita, M. Yoshimaru, M. Ino, "Supression of the MoS Transistor Hot Carrier Degradation Casued by Watdr Desorbed from Intermetal Dielectric", IEEE Symposium on VLSI Technology Digest of Technical Papers, Jun. 1992, pp. 96-97.
A.N. Saxena, K Ramkumar, S.K. Ghosh, "Stresses in TEOS Based SiO2 Films and Reliability of Multilevel Metalizations", Proceedings Ninth International VLSI Multilevel Interconnection Conference (VMIC, Jun. 1992, pp. 427-429.
V. Jamin, D. Praminik, "Impact of Inter Metal Oxide Structures and Nitride Passivaiton on Hot Carrier REliability of Sub-Micron MOS Devices", proceedings Ninth International VLSI Multilevel Interconnection Conference (VMIC), Jun. 1992, pp. 417-419.
N. Shimoyama, K. Machida, K. Murase, T. Tsuchiya, "Enhanced Hot-Carrier Degradation Due to Water in TEOS/O3-Oxide and Water Blocking Effect of ECR-SiO2", IEEE Symposium on VLSI Technology, Jun. 1992, pp. 94-95.
A. Hamada, T. Furusawa, E. Takeda, "A New Aspect on Mechanical Strress Effects in Scaled MOS Devices", IEEE Symposium on VLSI Technology Digest of Technical Papers, Jun. 1990 p. 113.
M. Noyori, T. Ishihara, H. Higuchi "Secondary Slow Trapping--A New Moisture Induced Instability Phenomenon in Scaled CMOS Devices", IEEE 20th Annual Proceedings Reliability 1982, p. 113.
J. Mitsuhashi, H. Muto, Y. Ohno, T. Matsukawa, "Effect of P-SiN Passivation Layer on Time-Dependent Dielectric Breakdown in SiO2", IEEE 25th Annual Proceedings Reliability Physics, Apr. 1987, pp. 60-65.
K.P. MacWilliams, L.E. Lowry, D.J. Swanson, J. Scarpulla, "Water-Mapping of Hot Carrier Lifetime Due to Physical Stress Effects", IEEE Symposium on VLSI Technology, Digest of Technical Papers, Jun. 1992, pp. 100-101.
J. Mitsuhashi, S. Kakao, T. Matsukawa, Mechanical Stress and Hydrogen Effects on Hot Carrier Injection, IEE-IEDM Tech Digest, International Electron Devices Meeting Dec. 1986, p. 386.
Y. Ohno, A. Ohsaki, T. Kaneoka, J. Mitsuhashi, M. Hirayama, T. Kato, "Effect of Mechanial Stress for Thin SiO2 Films in TDDB and CCST Characteristics", IEE 27th Annual Proceedings Reliability Physics, Apr. 1989, pp. 34-38.
W. Abadeer, W. Tonti, et al, "Bias Temperature Reliability of N+ and P+ Polysilicon Gates NMOSFETs and POMSFETs, "IEEE 31st Annual Proceedings Reliability, Aug. 1993, pp. 147-149.
K.O. Jeppson, C.M. Svensson "Negative bias stress of MOS devices at high electric fields and degradation of MNOS devices" Journal of Applied Physics V48, #5, May 1977 pp. 2004-2014.
R.T. Fuller, W.R. Richards, Y. Nissan-Cohen, J.C. Tsang P.M. Sandow, "The Effects of Nitride Layers On Surface Density and the Hot Electron Lifetime of Advanced CMOS Circuits" IEEE 1987, Custom Intefrated Circuits Conference, pp. 337-340.
S. Fujita, Y. Uemoto, A. Sasaki, "Trap Generation in Gate Oxide Layer of MOS Structures Encapsulated by Silicon Nitride", IEDM-IEEE 1985, pp. 64-67.
Stanley Wolf, "Silicon Processing for the VLSI Era", vol. 2 pp.132-133, 144-145, 164-165, 188-189, 194-195, 392-396.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

High tensile nitride layer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High tensile nitride layer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High tensile nitride layer will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-367589

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.