High-temperature superconducting random access memory

Details High-temperature superconducting random access memory High-temperature superconducting random access memory

1997-11-20

1999-08-24

Crane, Sara

Active solid-state devices (e.g., transistors, solid-state diode

Thin active physical layer which is

Tunneling through region of reduced conductivity

257 34, 257 36, 365162, 505190, H01L 2906

Patent

active

059427655

ABSTRACT:
In the random access memory utilizing an oxide high-temperature superconductor, a first high-temperature superconductor layer 1, a non-superconductor layer 2, a second high-temperature superconductor layer 3 and a non-superconductor layer 4 are formed on an insulated substrate. The first high-temperature superconductor layer 1 is formed in a first loop, forming a memory storage superconductor quantum interference device by two Josephson junctions and a control current line I.sub.WX (6) and a bias current line I.sub.WY (8) in order to store the flux quantum. The second high-temperature superconductor layer 3 is formed in a second loop, forming a reading superconducting quantum interference device by two Josephson junctions and a control current line I.sub.RX (5) and a bias current line I.sub.RY (7). By use of the characteristic where the output is occurred according to the polarity of the flux quantum held by the first loop, the writing and reading of the memory is done by a binary logic of "0" and "1", and functions as a random access memory.

REFERENCES:
patent: 4509146 (1985-04-01), Wang et al.
patent: 4601015 (1986-07-01), Ishida
patent: 4764898 (1988-08-01), Miyahara et al.
patent: 5227645 (1993-07-01), Shinada
patent: 5629889 (1997-05-01), Chandra et al.

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