Patent
1975-06-10
1977-08-16
Wojciechowicz, Edward J.
357 23, 357 59, 357 41, H01L 2348, H01L 2978, H01L 2702, H01L 2904
Patent
active
040429539
ABSTRACT:
A multi-layer integrated semiconductor circuit interconnection structure with a first layer formed of a refractory metal sandwich including outer layers of silicon and a core of refractory metal providing a high temperature low ohmic contact assembly, an insulating layer formed on the first layer, and a patterned metal layer formed on the insulating layer to interconnect with the refractory layer and semiconductor device to provide an integrated circuit assembly.
REFERENCES:
patent: 3475234 (1969-10-01), Kerwin et al.
patent: 3614547 (1971-10-01), May
patent: 3667008 (1972-05-01), Katnack
Micro Power Systems Inc.
Wojciechowicz Edward J.
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