High speed wafer sort and final test

Details High speed wafer sort and final test High speed wafer sort and final test

2003-03-20

2004-08-17

Zarneke, David A. (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

Reexamination Certificate

active

06777971

ABSTRACT:

BACKGROUND OF THE INVENTION
Integrated circuits are manufactured on a semiconductor wafer. Typically, hundreds of integrated circuits commonly referred to as dies are built on the same wafer. After wafer fabrication the wafer is cut into individual dies or chips. Each die is packaged by coupling bonding pads on the die to corresponding bonding pads on a substrate.
A substantial number of dies on the wafer may be defective. As each step of the semiconductor manufacturing process adds cost to the final product, it is beneficial to determine whether a particular die is operational at various steps of the manufacturing process. A wafer sort test is typically performed after wafer fabrication to determine faulty dies prior to cutting the wafer into individual dies. Typically, wafer sort tests include a functional test of the circuitry in the die.
The wafer sort test is performed by a tester coupled to a probe card. The tester generates test signals and transmits the test signals to dies on the wafer through the probe card which is coupled to the die to be tested. Each die on the wafer is tested by moving the wafer to couple the die to be tested to the probe card.
The probe card has a plurality of probe bonding pads corresponding to die bonding pads on the die. The wafer is moved toward the probe card until the probe bonding pads on the probe card are coupled to the die bonding pads on the die to be tested. Test results are transmitted from the die through the probe card to the tester to be analyzed by the tester.
Wafer sort tests typically include parametric tests and functional tests. A parametric test tests electrical characteristics (DC parameters) of the die. A functional test tests the operation of an electric circuit in the die. After a die is tested, the wafer is moved to position the next die to be tested under the probe card.
FIG. 1
illustrates a prior art probe card
118
in a wafer sort testing system. A wafer
100
includes a plurality of dies
102
with each die having a plurality of die bonding pads
108
. Each die
102
on the wafer is functionally tested by a tester
114
by coupling the die to a probe card
106
through probe needles
104
. The probe card
106
includes a plurality of probe bonding pads
108
corresponding to the die bonding pads
108
on the die. The tester
114
supplies electrical signals to the die through the probe card
106
and measures other electrical signals on the die. The tester
114
performs a functional test of the substrate by supplying an electrical signal through test channel
116
to a test pad
112
. Test pad
112
is coupled through trace
118
in the probe card
106
to one of the probe bonding pads
110
on probe card
106
. The electrical signal is supplied to the die
102
through probe needle
104
and die bonding pad
108
.
Typically, the operating speed of the tester is limited by frequency limitations due to the length of the probe needles
104
and cross-talk between the probe needles
104
. Probe needle length is typically about 1″. Wafer sort testers can operate up to 500 Mega Hertz (MHz) but typically operate at about 200 MHz because of these frequency limitations. However, semiconductor devices such as networking devices with high-speed transmitters and receivers operate at frequencies greater than 500 MHz. For example, in a switch which transfers data according to the ANSI T1X1.5 standard, commonly referred to as Synchronous Optical NETworking (SONET), the serial data Input/Output transfer rate is 3.125 Giga bits per second (Gbps).
SUMMARY OF THE INVENTION
A built in self test circuit which generates test patterns and compares them for accuracy is included in a die. A probe card includes high-speed interconnects which connect a respective output of a transmitter in the die to a respective input of a receiver in the die while the probe card is connected to the die. The high-speed interconnect allows the data path through the receiver and transmitter in the die to be tested at operational speed before the die is assembled into a package.
A method and apparatus for performing a wafer sort test is presented. A wafer includes a plurality of dies. Each die includes a plurality of die bonding pads and a built in self test circuit. At least one die bonding pad is coupled to an input of a receiver and at least another die bonding pad is coupled to an output of a transmitter. The built in self test circuit generates test data to be transmitted through the transmitter and analyzes the test data received at the input of the receiver. A probe card includes a plurality of probe bonding pads for coupling to the plurality of die bonding pads on the die. When the die is coupled to the probe card, the probe bonding pads corresponding to the receiver input and the transmitter output are coupled to corresponding die bonding pads. An interconnect in the probe card connects probe bonding pads to route test data transmitted from the transmitter to the receiver.
The test data may be transmitted and received at an operational speed greater than 500 MHZ. The test data may be a pseudo random bit sequence.
The built in self test circuit may also include framing logic which generates framing characters. The framing characters precede the pseudo random bit sequence in a frame. The pseudo random bit sequence may be stored in a payload of the frame and the framing characters may be Synchronous Optical NETwork (SONET) framing characters or Ethernet idle characters.


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