Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2000-11-13
2002-10-01
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
Reexamination Certificate
active
06459328
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a highly efficient voltage boosting circuit.
2. Description of the Related Art
A voltage boosting circuit is a circuit frequently used for generating another voltage from a power supply voltage, and more specifically the higher voltage than the power supply voltage. Generally, in the voltage boosting circuit, a capacitance element is charged from the power supply so that the output voltage is increased. Accordingly, the voltage boosting circuit can generate a boosted voltage having an absolute value greater than a power supply voltage Vcc.
A conventional example of the voltage boosting circuit will be described in more detail with reference to FIG.
1
and
FIGS. 2A
to E.
The conventional voltage boosting circuit is composed of N-channel transistors N
5
-
1
to N
5
-
8
and capacitors CP
5
-
1
to CP
5
-
8
. Clock signals CK
5
-
1
to CK
5
-
4
are supplied to the voltage boosting circuit. A terminal OUT-
5
-
1
is an output terminal for outputting the boosted voltage.
The operation of the voltage boosting circuit shown in
FIG. 1
will be described with reference to
FIGS. 2A
to E. Referring to
FIGS. 2A
to E, when the clock signal CK
5
-
2
goes to a high level in the state in which the clock signal CK
5
-
3
is at a low level as shown in
FIG. 2C
, the voltage at the gate of the transistor N
5
-
5
is boosted to a level sufficiently higher than the power supply voltage Vcc through the operation of the coupling capacitor CP
5
-
1
. This allows the capacitor CP
5
-
5
to be charged to the power supply voltage Vcc. At this time, the clock signal CK
5
-
4
is at low level so that the transistor N
5
-
6
remains turned off. Therefore, no change is transferred through the transistor N
5
-
6
.
Then, the clock signal CK
5
-
2
goes to the low level to turn off the transistor N
5
-
5
. As the clock signal CK
5
-
3
goes to the high level, the potential of the capacitor CP
5
-
5
is increased to the potential equal to twice of the power supply voltage Vcc when a loss caused by parasitic capacitance is negligible.
While the boosted level is maintained, the clock signal CK
5
-
4
goes to the high level so that the transistor N
5
-
6
is turned on. At this time, the clock signal CK
5
-
1
held at the low level. Thus, the voltage at the gate of the transistor N
5
-
6
is increased to a level higher than the power supply voltage. As a result, the charge stored in the capacitor CP
5
-
5
is transferred to the capacitor CP
5
-
6
. The voltages of the capacitors CP
5
-
7
and CP
5
-
8
are boosted in the same manner as described above, and the boosted voltage is finally outputted from the terminal OUT
5
-
1
.
As described above, if any loss caused by parasitic capacitance is negligible, the voltage boosting circuit can boost the input voltage to (the number of capacitance elements plus one) multiplied by the power supply voltage Vcc. Similar to the boosting operation of a positive voltage, the input voltage can be boosted in a negative direction.
However, in the above conventional voltage boosting circuit there are some problems in that current consumption is much and the boosting operation is slow. Particularly, the problems are severe when the output terminal is linked to a load capacitor. Such a case will be described below referring to FIG.
1
.
As the output terminal is linked to a large load capacitor, the voltage at the output terminal OUT
5
-
1
cannot be rapidly increased to a desired voltage even if the boosting operation is repeated. In this case, the voltage between the source and the drain in each of the switching elements (the transistors N
5
-
5
to N
5
-
8
) is hardly increased. Accordingly, the voltage at the output terminal continues to be lower than the boosted voltage by the capacitance elements (the capacitor CP
5
-
5
to CP
5
-
8
) of the four stages. In this state, therefore, driver elements for driving the clock signals CK
5
-
3
to CK
5
-
1
ill consume the current in vain. More specifically, while the voltage at the output terminal OUT
5
-
1
is as low as the power supply voltage Vcc, three of the boosting capacitance elements (the capacitor CP
5
-
5
to CP
5
-
8
) are unnecessary and will only increase the current consumption.
For the purpose to overcome the above problems, a voltage boosting circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 7-111095). In this reference, the efficiency of power usage is improved when the output voltage is low, so that the time of the boosting operation is shortened. The voltage boosting circuit is composed of booster cells and a switching circuit for switching the connection of the booster cells. The switching circuit is arranged between the booster cells. The booster cells are grouped into groups. The switching circuit connects the groups to the output terminal in parallel. In each group, one or more booster cells are connected in series. The number of booster cell groups, and the number of booster cells in the group are variable.
However, in the voltage boosting circuit disclosed in the above reference, the booster cells and the switching circuit are separately provided. Accordingly, the current consumption is still abundant.
In conjunction with the above description, a voltage boosting circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 2-179264). In this reference, the voltage boosting circuit is composed of a plurality of boosting blocks, switches, a voltage determining section and a circuit selecting section. Each of the plurality of boosting blocks is composed of a plurality of diodes connected in series between a power supply voltage input terminal and a boosting voltage output terminal or a circuit equivalent to the plurality of diodes, and a capacitor connected to a node between every two of the plurality of diodes. A desired boosted voltage is produced through a forward direction charge transfer operation by the diodes and the capacitors. The switches are provided between the power supply voltage input terminal and the boosting blocks, respectively. The voltage determining section determines an input voltage level at the power supply voltage input terminal. The circuit selecting section controls the switches based on the determining result of the voltage determining section to select ones of the boosting blocks.
Also, a non-volatile semiconductor memory is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 6-223588). In this reference, a plurality of basic circuit
20
for carrying out a voltage boosting operation is grouped into a plurality of groups. Clock signals &phgr;1 and &phgr;2 are supplied to each basic circuits
20
of a part of the groups from the start of the voltage boosting operation. The clock signals &phgr;1 and &phgr;2 are supplied to each basic circuit
20
of another part of the groups after a predetermined time passes since from the start of the voltage boosting operation. The above clock signals &phgr;1 and &phgr;2 are supplied to each basic circuit
20
of the remaining groups after a further predetermined time passes. Thus, in the non-volatile semiconductor memory which has a voltage boosting circuit, the increase of the chip area is suppressed the to the minimum. Also, the decrease of the boosted voltage can be prevented.
Also, a voltage boosting circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 11-110989). In this reference, the voltage boosting circuit has 4-phase clock signal. A drive clock signal is supplied to the gate of a boosting transistor the transistor N
1
provided between the gate Q
1
and the drain P
1
in a charge transfer transistor M
1
. The drive clock has the same timing as that at a node P
2
which is located at a predetermined number of stages from a node P
1
in a P
2
direction. For example, when the gate of the transistor the transistor N
1
is connected with a node P
4
, the charge transfer efficiency by the transistor the transistor N
1
can be improved.
SUMMARY OF THE INVENTION
Therefore, an objec
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