Radiant energy – Photocells; circuits and apparatus – Photocell controlled circuit
Reexamination Certificate
2001-04-09
2003-08-19
Le, Que T. (Department: 2878)
Radiant energy
Photocells; circuits and apparatus
Photocell controlled circuit
C250S2140RC
Reexamination Certificate
active
06608296
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a high-speed vision sensor having an image processing function.
BACKGROUND ART
High-speed image processing is required to operate high-speed robots in a factory automation (FA) system or the like. For example, when a robot is configured with a feedback loop between its vision sensor and its actuator, the actuator can be controlled in units of milliseconds. Accordingly, the image processing speed matching this speed is required. However, because the image processing speed in modern vision systems is limited by the video frame rate, the robot can only operate at low speeds matching the image processing speed. It is impossible to take full advantage of the robot's performing capability.
There are some high-speed CCD cameras that can take images at intervals of about one (1) millisecond. In these devices, the images are temporarily stored in memory and later read and processed. Therefore, the devices can be applied to such applications as image analysis. However, the devices have almost no real-time capability, and are not suitable for controlling robots or similar real-time applications.
In order to overcome these problems, institutes such as the Massachusetts Institute of Technology, the California Institute of Technology, and Mitsubishi Electric Corporation have been researching a vision chip that combines the image reading portion and the processing portion into one unit (“An Object Position and Orientation IC with Embedded Imager,” David L. Standley, Solid State Circuits, Vol. 26, No. 12, Dec. 1991, pp. 1853-1859, IEEE); “Computing Motion Using Analog and Binary Resistive Networks,” James Hutchinson, et al., Computer, Vol. 21, March 1988, pp. 52-64, IEEE); and “Artificial Retinas—fast versatile image processors,” Kazuo Kyuma, et al., Nature, Vol. 372, Nov. 10, 1994). However, these chips employ a fixed analog circuit that is easy to integrate. Accordingly, these circuits have such shortcomings as requiring subsequent-processing of output signals and a lack of universality. Hence, the type of image processing they can perform is limited to special applications.
Japanese Unexamined Patent Application Publication HEI-10-145680 has proposed a vision chip that is capable of performing universal image processing. This vision chip is provided with a processing element for each photodetector. An analog-to-digital converter is provided for each photodetector row. Therefore, the vision chip can reduce the processing time through parallel processing. The vision chip can also reduce the number of transmission lines between the photodetectors and the processing elements, achieving an optimal integration level for both.
However, since this vision chip is configured to use the processing elements themselves when transferring data thereto, processing cannot be performed during image transfers. It is noted that it is necessary to perform image processing over a plurality of images in order to detect the shape of objects or to detect movement. Since conventional methods temporarily read a plurality of images into memory before processing, such processing cannot be performed in real-time.
DISCLOSURE OF THE INVENTION
In view of the foregoing, it is an object of the present invention to provide a multi-pixel high-speed vision sensor which has a simple circuit construction and which is capable of performing efficient high-speed calculations even over a plurality of images.
In order to attain the object, the high-speed vision sensor of the present invention comprises: at least one photodetector array, each having a plurality of photodetectors which are arranged two-dimensionally in a plurality of rows and in a plurality of columns; an analog-to-digital converter array having a plurality of analog-to-digital converters which are arranged one-dimensionally such that each analog-to-digital converter corresponds to one row in the at least one photodetector array, each analog-to-digital converter converting, into digital signals, analog signals which are successively outputted from the photodetectors in the corresponding row; a parallel processing system, including a parallel processing element array and a shift register array, the parallel processing clement array having a plurality of processing elements which are arranged two-dimensionally in a plurality of rows and in a plurality of columns and in one-to-one correspondence with the plurality of photodetectors in the at least one photodetector array, each processing element performing a predetermined calculation on digital signals transferred from the analog-to-digital converter array, the shift register array having a plurality of shift registers which are disposed in one-to-one correspondence with the plurality of analog-to-digital converters and in one-to-one correspondence with the plurality of rows of processing elements, each shift register successively transferring digital signals, which are received from the corresponding analog-to-digital converter and which are equivalent to signals outputted from the photodetectors in a corresponding photodetector row, to predetermined processing elements in the corresponding row; and a control circuit controlling the photodetector array and the analog-to-digital converter array to output digital signals for a single frame and controlling the shift register array to transfer the digital signals of the single frame to the parallel processing element array, and thereafter controlling the photodetector array and the analog-to-digital converter array to output digital signals for the next frame and controlling the shift register array to transfer the digital signals of the next frame to the parallel processing element array, while simultaneously controlling the parallel processing element array to perform the predetermined calculation onto the single frame.
According to the present invention, the plurality of processing elements are provided in one to one correspondence with the plurality of photodetectors. It is therefore possible to perform high-speed image processing through parallel processing. Additionally, the shift registers are used as being dedicated to transferring data for processing. Accordingly, image processing can be performed during the transfer process. Image processing can be performed efficiently by reducing the wait time for both of the transfer process and the calculating process, thereby reducing the overall processing time. It is therefore possible to achieve a pipeline operation. It is possible to perform high-speed image processing, and particularly real-time processing. An analog-to-digital converter is provided for each row. Accordingly, the total number of transmission paths can be reduced.
When the high-speed vision sensor has a plurality of photodetector arrays, the parallel processing system may preferably include, in correspondence with each processing element row, a plurality of lines of shift registers, the number of the plurality of lines being equal to the number of the plurality of photodetector arrays.
With this construction, the plurality of lines of shift registers are provided for transferring, to each row of processing elements, data from the corresponding row of photodetectors in the plurality of photodetector arrays. Accordingly, even when the high-speed vision sensor has plural photodetector arrays, image signals from the plural photodetector arrays can be transferred independently from one another, thereby requiring no extra time for the transfer process than when the high-speed vision sensor has only one photodetector array. Therefore, the image processes, including the calculating processes, can be performed at a high rate of speed.
The plurality of photodetector arrays may be disposed at positions different from one another. The control circuit may include: a parallel processing control portion controlling the respective lines of shift registers to transfer images which are taken at different positions and outputted from the corresponding photodetector arrays, and controlling the parallel processing system t
Ishikawa Masatoshi
Toyoda Haruyoshi
Hamamatsu Photonics K.K.
Le Que T.
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