High-speed variable-length decoder

Details High-speed variable-length decoder High-speed variable-length decoder

1992-06-04

1993-09-14

Williams, Howard L.

Coded data generation or conversion

Digital code to digital code converters

To or from variable length codes

341 65, H03M 740

Patent

active

052453383

ABSTRACT:
A variable-length decoder is disclosed which includes a decoder part (101) and an interface part (102). The decoder part includes two decoder latches (110 and 111) which store consecutive sequences of bits, which are each equal in length to the maximum-length codeword. A decoder barrel shifter (109) provides an output decoding window of a subsequence of bits in the two latches equal in length to the maximum-length codeword. This subsequence is supplied to a memory device (116) which provides a corresponding decoded codeword output and codeword-length output for each subsequence that begins with the first bit of a variable-length to be decoded. At each clock cycle, the same subsequence is supplied to the input of the first decoder latch and the decoder barrel shifter is shifted by the codeword-length of the previous word so that the decoder barrel shifter output subsequence always begins with the first bit of the word to be decoded. The interface part supplies the second decoder latch. The interface part includes an interface barrel shifter (127) which is supplied from two interface latches (125 and 126) which in turn are provided input from a buffer (106) which stores the input bit stream in fixed-length segments. An accumulator (130, 131) accumulates the codeword-lengths of decoded codewords and, at each clock cycle, shifts the output of the interface barrel shifter in accordance with the accumulated lengths so that the bits in its output window are consecutive with the bits in the output window of the decoder barrel shifter. When the accumulated codeword-lengths indicate that all the bits in the first interface latch have been transferred to the decoder part, then a new segment is retrieved from the buffer and stored in the second interface latch while the previous segment in that latch is transferred into the first interface latch.

REFERENCES:
patent: 3675212 (1972-07-01), Raviv et al.
patent: 3717851 (1973-02-01), Cocke et al.
patent: 5032838 (1991-07-01), Murayama et al.
patent: 5055841 (1991-10-01), Cordell
patent: 5162795 (1992-11-01), Shirota
J. W. Peake, "Decompaction", IBM Technical Disclosure Bulletin, vol. 26, No. 9, Feb. 1984, pp. 4794-4797.

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