High speed, universal polarity full adder which consumes...

Details High speed, universal polarity full adder which consumes... High speed, universal polarity full adder which consumes...

2007-02-27

2007-02-27

Mai, Tan V. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S703000

Reexamination Certificate

active

10014287

ABSTRACT:
A low power, high speed full adder cell is described. This cell supports all possible combinations of active high/active low input/output signal polarity (32 different combinations), without adding extra inverters or extra transistors. The cell makes liberal use of complementary metal oxide semiconductor (CMOS) transmission gates in order to minimize the number of transistors used, and to minimize their stacking. This significantly decreases the total transistor gate area consumed, resulting in minimal power dissipation and minimal cell size.

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patent: 4866658 (1989-09-01), Mazin et al.
patent: 4920509 (1990-04-01), Hmida et al.
patent: 5875124 (1999-02-01), Takahashi

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