High speed unitransition input buffer

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating

Patent

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Details

327299, 327176, G06F 104

Patent

active

060231815

ABSTRACT:
A two stage input buffer substantially reduces propagation delay by triggering only off of the rising edge of the external clock signal, eliminating a pulse generator, and setting the pulse width via feedback through a fixed delay. An unbalanced driver reduces capacitance on the N-channel transistor. In a memory application, such as in a synchronous dynamic random access memory, access time is improved, margin is advantageously added to the hold time requirement, and driver fan out capabilities are improved.

REFERENCES:
patent: 5477180 (1995-12-01), Chen
patent: 5828249 (1998-10-01), Sessions

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