High speed TTL clock input buffer circuit which minimizes power

Details High speed TTL clock input buffer circuit which minimizes power High speed TTL clock input buffer circuit which minimizes power

1983-12-07

1986-03-25

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307452, 307481, 307246, 307269, 307579, H03K 19096

Patent

active

045786011

ABSTRACT:
A buffer circuit is provided for buffering an input clock signal having TTL voltage levels to provide an output clock signal having MOS voltage levels. A reference voltage portion provides an accurate bias voltage to a first node. A voltage translation portion is coupled between an input and the first node. An inverter portion has a first input connected to the first node, a second input for receiving the input clock signal, and an output for providing the output clock signal. A clamping portion is connected to the first node to minimize the bias voltage potential.

REFERENCES:
patent: 4048518 (1977-09-01), Koo
patent: 4284905 (1981-08-01), Rosenzweig
patent: 4379974 (1983-04-01), Plachno

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