High speed trunk interface with concurrent protocol handlers

Details High speed trunk interface with concurrent protocol handlers High speed trunk interface with concurrent protocol handlers

1986-10-31

1988-03-29

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 94, H04Q 1104

Patent

active

047349085

ABSTRACT:
A digital trunk interface utilizing the first protocol handler to signal the start of a packet and a second protocol handler responsive to the packet delayed to initiate the storage of the packet internally to the digital trunk interface. The digital trunk interface comprises a microprocessor and two universal synchronous asynchronous receiver transmitter (USART) circuits. One USART is directly connected to the incoming digital trunk and is utilized to inform the microprocessor when a packet is first received. The second USART receives the packet delayed by a predefined amount of time from the digital trunk. The microprocessor is responsive to the signal from the first USART that a packet has been received to perform the necessary administrative functions for receipt of the packet by the second USART.

REFERENCES:
patent: 4227075 (1980-10-01), Holland
patent: 4412326 (1983-10-01), Limb
patent: 4700340 (1987-10-01), Beranek et al.

Affiliated with

Also associated with

Rating

High speed trunk interface with concurrent protocol handlers does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High speed trunk interface with concurrent protocol handlers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed trunk interface with concurrent protocol handlers will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1093750