High speed transmission system with clock inclusive balanced...

Details High speed transmission system with clock inclusive balanced... High speed transmission system with clock inclusive balanced...

2001-12-17

2004-02-10

Jeanglaude, Jean Bruner (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

To or from 'n' out of 'm' codes

C341S050000

Reexamination Certificate

active

06690309

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to data transmission systems, and more particularly to high speed data transmission systems in which data values may be transmitted with a clock signal.
BACKGROUND OF THE INVENTION
The increasing need for faster data communication rates has led to corresponding needs for faster transmission of data between system components. Networking hardware is but one of the numerous applications in which such increased speed is needed. Within a high-speed router data is typically transmitted between one or more integrated circuits. If such inter-chip data transmission speeds can be increased (e.g., in the range of 1 gigabits/second per pin), the overall speed/bandwidth of the connection between integrated circuits may also be increased.
Data transmission systems can include bus connections, in which bus lines may be commonly shared between multiple devices, and point-to-point connections, in which a one device is connected to another by one or more direct data transmission lines. Bus oriented systems may have a number of drawbacks. Due to the number of devices attached to the bus lines (because they are shared among multiple devices) the inherent capacitance attached to the lines may be large, limiting the speed at which the lines may be driven. Larger lines may consume higher amounts of power, as well. Still further, because a bus is commonly shared, some form of arbitration is typically included to enable one device to have control of the bus at a given time. Such arbitration needs can add to the complexity of the system. It is also noted that the inclusion of a common bus on a circuit board, or the like, requires a dedicated amount of area. This can work against the goal of manufacturing systems that are as physically compact as possible.
Bus and point-to-point approaches may have common drawbacks. One such drawback is susceptibility to “ground bounce.” Ground bounce may occur due to sudden current draws on a power supply. In arrangements where signal lines are situated over a ground plane, rapid fluctuations in current may result in noise radiating from such a ground plane. In addition, or alternatively, due to inherent inductance in a power supply, a rapid fluctuation in current can cause a ground or supply voltage to vary (i.e., bounce). This may adversely affect data sensing operations that may depend on a stable supply voltage, or reference voltages generated from such supply voltages.
Yet another common drawback can arise in cases where a system includes differential type receiver circuits that rely on a reference voltage to distinguish between logic values. Circuits for generating such reference voltages can be complex. “Band-gap” reference voltage generators, and the like, represent but one example of a more complex reference voltage generating circuit. In many cases, reference voltage generating circuits must be designed to account for temperature, process and other variations. In addition, in many cases such circuits can be dependent upon a particular supply voltage (i.e., are not supply voltage independent).
Typically, transmission systems can rely on some sort of clock (or strobe) signal to extract information from a data signal. Clock signals may be supplied separately, or may be encoded within a data signal. A drawback to encoded data signals can be ancillary circuitry that may be necessary. As but one example, in many cases a phase lock loop (PLL) may have to be included to recover an embedded clock, and thereby enable data to be extracted. Still further, a data stream for a signal with an embedded clock may require a certain number of transitions within a given time period.
Various conventional examples will now be described with reference to a number of figures. Referring now to
FIG. 18
, a conventional data transmission system, that includes a serial to parallel conversion step, is shown in a block diagram and designated by the general reference character
1800
. A system
1800
may receive one or more input lines
1802
-
0
to
1802
-n on which data may be transmitted in serial form. Such serial data may include an embedded clock. Serial data may be stored in corresponding storage circuits
1804
-
0
to
1804
-n, or like. Once a predetermined number of bits have been accumulated, such bits may be transmitted, in parallel from such storage circuits (
1804
-
0
to
1804
-n) onto parallel output lines
1806
-
0
to
1806
-n. In addition to the various drawbacks described above, a conventional system
1800
also introduces the undesirable delay involved in converting serial data to parallel form. More particularly, a conversion to 8 parallel bits can require an 8 cycle latency.
Another conventional approach is shown in FIG.
19
.
FIG. 19
shows a conventional system
1900
in which data may be transmitted in parallel along input lines
1902
-
0
to
1902
-n. Each input line (
1902
-
0
to
1902
-n) may be received at the input of a corresponding differential amplifier (
1904
-
0
to
1904
-n). Differential amplifiers (
1904
-
0
to
1904
-n) may distinguish between logic levels by amplifying differences between a reference voltage and an input line potential. A drawback to a parallel approach, such as that shown in
FIG. 19
, can be susceptibility to noise effects due to ground bounce, or the like. More particularly, a large majority of data signals may have the same logic level, generating a fluctuation in current and the corresponding adverse consequences noted above.
Additional drawbacks to a conventional case such as that shown in
FIG. 19
can be the difficulty in generating a robust reference voltage.
Referring now to
FIG. 20
, a block diagram of a third conventional
2000
case is shown. A system according to a third embodiment may include a transmitting driver
2002
that can drive an input line
2004
between a voltage Vdrive and ground. An input line
2004
may be provided to one input of a receiving differential amplifier
2006
. A second input to differential amplifier
2006
can be a reference voltage Vref, which may be ideally Vdrive/
2
. Termination resistance Rtx and Rrx may also be included to meet predetermined line impedance values for minimizing adverse transmission line effects.
The example of
FIG. 20
may include some of the same drawbacks as that of FIG.
19
. In particular, having unbalanced data values may generate noise, and the generation of a reference voltage may be complicated and/or not necessarily supply independent.
In light of the above, it would desirable to arrive at a data transmission system that may transmit data between two points without incurring the drawbacks of ground bounce noise and/or similar adverse effects. It would also be desirable to arrive at a system that is not subject to the constraints of conventional systems that may employ a separately generated reference voltage.
It would also be desirable to arrive at a data transmission system that may meet other additional capabilities.
An important system capability can be the ability to test a system or component for certain parameters. That is, while various system components may include particular operating specifications, once such components are assembled it can be difficult to test the operation of such systems. In a data transmission system, it can be valuable to determine how a system or component may operate under adverse condition that can result in additional noise and/or variations in a reference voltage. However, it can be difficult to introduce such conditions in order to actually test a system or component.
In systems that can operate according to a clock signal, an important feature can be the ability to determine signal skew. Signal skew, as related to data transmission systems, can include differences between a data value transition and an ideal transition, such as that of a clock signal. Determining signal skew of a system may allow for a system to be adjusted for better performance, and allow for a better understanding of the operational limitations of a system.
Thus, in light of the above discu

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