High-speed transmission system having a low latency

Details High-speed transmission system having a low latency High-speed transmission system having a low latency

2005-11-22

2005-11-22

Patel, Jay K. (Department: 2637)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

C356S329000, C356S329000, C370S395620

Reexamination Certificate

active

06968025

ABSTRACT:
In addition to a first transmitter circuit, a plurality of transmission lines and a first data processing circuit in the receive side, so as to cause a DLL circuit to be regulated that regulates timing of a sampling clock of the data signal, a second first transmitter circuit, a transmission line and a second data processing circuit are provided, when a second specific signal string is sent, a regulation start signal string is caused to be distributed by the second data processing circuit, regulation is caused to be made for a DLL circuit of the first data processing circuit by a regulation signal string, the data starting with the bit next to a first specific signal string detected in the data signal is written into a m-address n-bit FIFO circuit, simultaneously a read address synchronized with a system clock is generated from a third specific signal string that came to the second data processing circuit, whereby the data is recovered.

REFERENCES:
patent: 6522684 (2003-02-01), Okubo et al.
patent: 6775342 (2004-08-01), Young et al.
patent: 6788754 (2004-09-01), Liepe
patent: 2001/0033630 (2001-10-01), Hassoun et al.
patent: 11-340839 (1999-12-01), None
patent: 2000-216744 (2000-08-01), None

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