Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data
Reexamination Certificate
2008-09-16
2008-09-16
Lugo, David B (Department: 2611)
Pulse or digital communications
Synchronizers
Synchronizing the sampling time of digital data
C375S219000
Reexamination Certificate
active
10930579
ABSTRACT:
A high speed transceiver operable to receive lower data rate transmissions includes an oversampling module, an aligning module, a selecting module, and a memory module. The oversampling module is operably coupled to oversample an n-bit data word at an oversampling rate of m to produce an m by n bit oversampled data word, wherein the n-bit data word is received at a first data transmission rate that is less than a serial bit rate of the high speed transceiver. The transition boundary module is operably coupled to determine transition boundary data of the m by n bit oversampled data word in accordance with a clock of the high speed transceiver to produce transition boundary data. The selecting module is operably coupled to select representative bits in accordance with the transition boundary data to produce a recovered data word. The memory module is operably coupled to store the recovered data word.
REFERENCES:
patent: 4280224 (1981-07-01), Chethik
patent: 4933959 (1990-06-01), Knechtel
patent: 6128680 (2000-10-01), Sallee
patent: 6711221 (2004-03-01), Belotserkovsky et al.
patent: 7089444 (2006-08-01), Asaduzzaman et al.
patent: 7167534 (2007-01-01), Nakamura
patent: 7197098 (2007-03-01), Johnson
patent: 7257183 (2007-08-01), Dally et al.
patent: 2003/0190006 (2003-10-01), Nagano
patent: 2006/0062327 (2006-03-01), Dally
U.S. Appl. No. 10/771,210, filed Feb. 3, 2004, Huang.
Xilinx, Inc.; “Data Recovery,” Nick Sawyer, Application Note XAPP224 (v2.3), Mar. 4, 2004, pp. 1-7, available from Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124.
Razavi, Behzad, Monolithic Phase-Locked Loops and Clock Recovery Circuits, Theory and Design, IEEE Press, 1996, Part 5. AT&T Bell Laboratories, 11 pages, ISBN 0-7803-1149-3.
UG024, “RocketIO Transceiver User Guide”, Feb. 22, 2007, Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124.
U.S. Appl. No. 11/035,613, filed Jan. 14, 2005, Bataineh, Khaldoun, et al., entitled, “Receiver Operable to Receive Data at a Lower Data Rate”, Xilinx, Inc. 2100 Logic Drive, CA. 95124.
Razavi, Behzad, Monolithic Phase-Locked Loops and Clock Recovery Circuits, Theory and Design, IEEE Press, 1996, Part 5. AT&T Bell Laboratories, 11 pages, ISBN 0-7803-1149-3.
UG024, “RocketlO Transceiver User Guide”, Feb. 22, 2007, Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124.
Chuang Jerry
Huang Dai
Lugo David B
Markison Timothy W.
XILINX Inc.
LandOfFree
High speed transceiver receiving lower rate data does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High speed transceiver receiving lower rate data, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed transceiver receiving lower rate data will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3949731