High speed transceiver operable to receive lower data rate...

Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data

Reexamination Certificate

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C375S219000

Reexamination Certificate

active

10771210

ABSTRACT:
A high speed transceiver operable to receive lower data rate transmissions includes an oversampling module and a data recovery system. The oversampling module is operably coupled to oversample a unique alignment sequence and data of a data stream received at a first data transmission to produce an oversampled unique alignment sequence and oversampled data, respectively, wherein the first data transmission rate is less than a serial bit rate of the high speed transceiver. The data recovery system is operably coupled to: compare a portion of the oversampled unique alignment sequence with an expected oversampled partial alignment sequence; when the comparing the portion of the oversampled unique alignment sequence with the expected oversampled partial alignment sequence is favorable, determine one of a plurality of word alignments for the data stream based on the portion of the oversampled unique alignment sequence; and recover aligned data at the first data transmission rate from the oversampled data based on the one of the plurality of word alignments.

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U.S. Appl. No. 10/930,579, filed Aug. 31, 2004, Chuang, Jerry , et al., entitled, “High Speed Transceiver Receiving Lower Rate Data”, Xilinx, Inc., 2100 Logic Drive, CA 95124.
U.S. Appl. No. 11/035,613, filed Jan. 14, 2005, Bataineh, Khaldoun, et al., entitled, “Receiver Operable to Receive Data at a Lower Data Rate”, Xilinx, Inc., 21000 Logic Drive, CA 95124.
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XAPP224 (v2.3), Application Note, Sawyer, Nick, Data Recovery, Mar. 4, 2004, pp. 1-7, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.

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