Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data
Reexamination Certificate
2008-09-16
2008-09-16
Lugo, David B (Department: 2611)
Pulse or digital communications
Synchronizers
Synchronizing the sampling time of digital data
C375S219000
Reexamination Certificate
active
10771210
ABSTRACT:
A high speed transceiver operable to receive lower data rate transmissions includes an oversampling module and a data recovery system. The oversampling module is operably coupled to oversample a unique alignment sequence and data of a data stream received at a first data transmission to produce an oversampled unique alignment sequence and oversampled data, respectively, wherein the first data transmission rate is less than a serial bit rate of the high speed transceiver. The data recovery system is operably coupled to: compare a portion of the oversampled unique alignment sequence with an expected oversampled partial alignment sequence; when the comparing the portion of the oversampled unique alignment sequence with the expected oversampled partial alignment sequence is favorable, determine one of a plurality of word alignments for the data stream based on the portion of the oversampled unique alignment sequence; and recover aligned data at the first data transmission rate from the oversampled data based on the one of the plurality of word alignments.
REFERENCES:
patent: 4280224 (1981-07-01), Chethik
patent: 4933959 (1990-06-01), Knechtel
patent: 6128680 (2000-10-01), Sallee
patent: 6711221 (2004-03-01), Belotserkovsky et al.
patent: 7089444 (2006-08-01), Asaduzzaman et al.
patent: 7167534 (2007-01-01), Nakamura
patent: 7197098 (2007-03-01), Johnson
patent: 7257183 (2007-08-01), Dally et al.
patent: 2003/0190006 (2003-10-01), Nagano
patent: 2006/0062327 (2006-03-01), Dally
Razavi, Behzad, Monolithic Phase-Locked Loops and Clock Recovery Circuits, Theory and Design, IEEE Press, 1996, Part 5. AT&T Bell Laboratories, 11 pages, ISBN 0-7803-1149-3.
UG024, “RocketIO Transceiver User Guide”, Feb. 22, 2007, Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124.
XAPP224 (v2.3) , Application Note, Sawyer, Nick, Data Recovery, Mar. 4, 2004, pp. 1-7, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.
U.S. Appl. No. 10/930,579, filed Aug. 31, 2004, Chuang, Jerry , et al., entitled, “High Speed Transceiver Receiving Lower Rate Data”, Xilinx, Inc., 2100 Logic Drive, CA 95124.
U.S. Appl. No. 11/035,613, filed Jan. 14, 2005, Bataineh, Khaldoun, et al., entitled, “Receiver Operable to Receive Data at a Lower Data Rate”, Xilinx, Inc., 21000 Logic Drive, CA 95124.
Razavi, Behzad, Monolithic Phase-Locked Loops and Clock Recovery Circuits, Theory and Design, IEEE Press, 1996, Part 5. AT&T Bell Laboratories, 11 pages, ISBN 0-7803-1149-3.
UG024, “RocketIO Transceiver User Guide”, Feb. 22, 2007, Xilinx, Inc. 2100 Logic Drive, San Jose, CA 95124.
XAPP224 (v2.3), Application Note, Sawyer, Nick, Data Recovery, Mar. 4, 2004, pp. 1-7, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.
Liu Justin
Lugo David B
Markison Timothy W.
XILINX Inc.
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