High-speed time-to-digital converter

Details High-speed time-to-digital converter High-speed time-to-digital converter

2008-03-03

2010-10-05

Mai, Lam T (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C327S269000

Reexamination Certificate

active

07808418

ABSTRACT:
Techniques for enabling a time-to-digital (TDC) to sample with sub-inverter delay resolution are disclosed. In an embodiment, the inputs to a differential D-Q flip-flop in the TDC are coupled to a single-ended signal and a delayed and inverted version of that signal to allow time interpolation of the signal. Further disclosed are techniques to balance the loads of a first delay line and a complementary delay line within the TDC.

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Levine et al: “High-resolution flash time-to-digital conversion and calibration for system-on-chip testing Embedded microelectronic systems: status and trends (Part2)” IEEE Proceedings: Computers and Digital Techniques, IEEE, GB, vol. 152, No. 3, May 6, 20.
International Search Report—PCT/US09/035908—International Search Authority—European Patent Office—Jun. 8, 2009.
Written Opinion—PCT/US09/035908—International Search Authority—European Patent Office—Jun. 8, 2009.

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