Electrical transmission or interconnection systems – Personnel safety or limit control features – Interlock
Patent
1991-10-21
1994-05-10
Zazworsky, John
Electrical transmission or interconnection systems
Personnel safety or limit control features
Interlock
307494, H03K 524, H03K 1704
Patent
active
053110714
ABSTRACT:
The present invention provides a high speed, all CMOS comparator utilizing positive feedback and DC voltage clamping. The circuit comprises two source-coupled PMOS transistors with their sources coupled to a current source or a supply voltage. A third PMOS transistor is coupled between the source of the first PMOS transistor and a terminal of a current mirror. The gate of this third PMOS transistor is coupled to the output node in such a way as to provide positive feedback to the circuit. As the negative input voltage becomes lower than the positive input voltage, the current passing through the second PMOS transistor increases and the current passing through the first PMOS transistor decreases. As the output node increases in voltage, the equivalent resistance of the third PMOS transistor increases, thus decreasing the current through the first PMOS transistor. This acts to increase the current being provided to the output node and increases the drive characteristics of the circuit. As a further improvement to the circuit, a voltage-clamping device is included in the design.
REFERENCES:
patent: 3857047 (1974-12-01), Knight
patent: 4438349 (1984-03-01), Shoji
Silicon Systems Inc.
Zazworsky John
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