High speed testing for programmable logic devices

Details High speed testing for programmable logic devices High speed testing for programmable logic devices

1990-07-31

1992-10-27

Atkinson, Charles E.

Excavating

371 213, G01R 3128

Patent

active

051595990

ABSTRACT:
A shift register used to shift programming and test data into a programmable logic device is modified so that each bit thereof can be directly set or reset. Control signals can be used to directly place the required test patterns into the shift register. A memory connected to the shift register, and associated logic, provides a means for testing whether data was accurately written to the array without shifting any data off of the device.

REFERENCES:
patent: 4766569 (1988-08-01), Turner et al.
patent: 4841525 (1989-06-01), Liesko et al.
patent: 4872168 (1989-10-01), Aadsen et al.
patent: 4958345 (1990-09-01), Fujisaki
patent: 5060230 (1991-10-01), Arimoto et al.

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