High speed tester with narrow output pulses

Details High speed tester with narrow output pulses High speed tester with narrow output pulses

2002-09-17

2004-08-03

Tang, Minh N. (Department: 2829)

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

With rotor

C324S765010, C324S076470, C327S176000, C327S291000, C714S724000

Reexamination Certificate

active

06771061

ABSTRACT:

CROSS-REFERENCES TO RELATED APPLICATIONS
Not Applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable.
REFERENCE TO MICROFICHE APPENDIX
Not Applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to automatic test equipment for testing electronic devices and more particularly to testing devices that operate with high speed digital signals.
2. Description of Related Art
Automatic test equipment is widely used to test semiconductor components during their manufacture. The automatic test equipment generates stimulus signals and measures responses from a device under test. The responses are compared to the expected responses from a fully functioning chip to determine whether the device under test is fully functional.
The automatic test equipment is programmed with a pattern that represents the stimulus and expected data for a device under test. Different kinds of devices under test will require different patterns for testing. Thus, the automatic test equipment must be flexible enough to generate a wide range of signals that are compatible with the types of signals many types of chips generate or receive.
FIG. 1
shows a prior art test system in simplified block diagram form. The system includes a tester body
110
and a computer work station
112
that controls the operation of the tester body and provides a user interface.
Within tester body
110
, there are multiple copies of circuitry called a channel
114
. Each channel
114
generates or measures a signal on one lead of a device under test. A channel
114
includes a pattern generator
120
, a timing generator
122
a failure processor
124
, a formatter
126
, a driver
128
and a comparator
130
.
Pattern generator
120
stores the pattern that defines the data that is to be applied or is expected during each cycle of tester operation. The data specifies whether the tester is to drive data or measure data during that cycle. The pattern also includes information specifying the data value, such as a logic 1 or a logic 0.
Additionally, the format of the signal must be specified. For example, some semiconductor devices represent a logical 1 by having a signal line at a high voltage during an entire cycle. Other chips represent a logical 1 by changing the voltage on a signal line during a cycle. Still others represent a logical 1 by a voltage pulse on a line during the cycle. Further, where a voltage transition during the cycle is used to represent a signal, the time at which that transition occurs might be different for different chips under test.
Modern testers are sufficiently flexible that they can be programmed for almost any signal format. To achieve this flexibility, the tester includes a timing generator
122
. The timing generator generates what are known as “edge” signals. These are signals that change state at a time that can be programmed into the timing generator.
The edge signals are combined by a formatter
126
to produce an output signal of the desired shape. For example, to create a pulse that starts 0.5 nsec after the start of a cycle and has a width of 1 nsec, one of the edge signals would be programmed to occur 0.500 nsec after the start of the cycle. Another edge signal would be programmed to occur at 1.5 nsec after the start of the cycle. The formatter would combine these signals to create the desired signal to be applied to driver
128
. Driver
128
produces the signal that is applied to the device under test.
More specifically, formatter
126
uses the first edge to define when driver
128
is turned on and the second edge to define when driver
128
is turned off. Traditionally, the circuit that combines the edges is an S-R flip-flop. An S-R flip-flop has a Set input and a Reset input. While a logic high signal is applied to the Set input, the output of the flip-flop is high. While a logic high is applied to the Reset input, the output of the flip-flop is low. While both the Set and Reset inputs are low, the S-R flip-flop holds its state.
In a tester, the data in the pattern generator
120
controls which edges are applied to the flip flop in each cycle. For example, in a cycle in which the channel
114
should output a signal that is goes high at 0.5 nsec and low at 1.5 nsec, the tester will gate an edge to the S input of the flip flop that goes high at 0.5 nsec. Separately, an edge that goes high at 1.5 nsec is gated to the R input of the flip flop.
Because there are multiple edge signals that can all be programmed to occur at different times, the tester can be programmed to generate nearly any type of waveform. Limitations arise, though, when it is desired to generate a very fast signal because such signals have short periods (i.e. narrow pulse widths).
Timing generator
122
is limited in how narrow a pulse it can generate for an edge signal. If the width of a set signal from timing generator
122
is wider than the desired width of the output pulse to be generated by tester
110
, that means that the Reset signal will be asserted before the end of the Set signal. In other words, both the Set and Reset inputs to the S-R flip-flop will be asserted simultaneously. A conventional S-R flip-flop does not have a determinate output state when both the Set and Reset inputs are asserted. Therefore, we have recognized the need for a unique S-R flip-flop that can respond appropriately to having both its Set and Reset inputs asserted simultaneously. We will describe this unique S-R flip-flop as an SRM flip-flop below.
Even with our inventive flip-flop circuit that allows both the Set and Reset inputs to be asserted simultaneously, we have identified a second limitation in generating high frequency signals. When using a conventional format circuit consecutive output pulses can not occur at an interval narrower than the width of the edge signals. Otherwise, the Set signal used to define the beginning of one output pulse will still be asserted when it is time to assert the Set signal to define the beginning of the next pulse.
In part, we have avoided this second limitation by generating multiple groups of edge signals. Each group of edge signals can be used to define a pulse. For example, there might be “Odd” Set and Reset signals and “Even” Set and Reset signals. The odd signals would be used to define the beginning and end of output pulses 1, 3, 5 . . . . The even signals would be used to define the beginning and end of output pulses 2, 4, 6 . . . . Such an approach is sometimes called interleaving or multiplexing the edges.
U.S. Pat. No. 5,321,700 to Brown et al. is an example of an interleaved tester, and is hereby incorporated by reference. However, using different edge signals to generate successive output pulses does not avoid the limitation that a subsequent Set signal can not occur until the first Set signal is no longer asserted. As will be described below, we have invented a way to generate successive output pulses that are spaced apart by an interval shorter than the duration of a Set signal.
BRIEF SUMMARY OF THE INVENTION
With the foregoing background in mind, it is an object of the invention to provide an automatic test system that operates at high data rates.
To achieve the foregoing object, as well as other objectives and advantages, the tester is provided with a plurality of edge groups that can be used to generate successive output signals. The formatter is constructed with state based pulse shaping circuitry that outputs a pulse that has a duration determined by the time between the rising edge of a set signal and the rising edge of a reset signal. The state based pulse shaping circuitry operates even if the Set signals and Reset signals overlap or if the Set or Reset signals in different edge groups overlap.


REFERENCES:
patent: 5003194 (1991-03-01), Engelhard
patent: 5258968 (1993-11-01), Matsuda et al.
patent: 5293079 (1994-03-01), Knoch
patent: 5321700 (1994-06-01), Brown et al.
patent: 6291981 (2001-09-01), Sartschev
Sailesh R. Maskai, et al., “Synthesis Techniques for CMOS Folded Source-Coupled Logic Circuits”,

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