High-speed synchronous write control scheme

Details High-speed synchronous write control scheme High-speed synchronous write control scheme

1997-12-22

2000-04-18

Tran, Andrew Q.

Static information storage and retrieval

Addressing

Sync/clocking

36518905, 365202, 365190, G11C 800

Patent

active

06052328&

ABSTRACT:
The present invention provides a method and apparatus that accomplishes a high performance, random read/write SDRAM design by synchronizing the read and write operations at the data line sense amplifier. This enables the design to perform random read and write operations without varying cycle time issues or unbalanced margin issues. The data lines are used as bi-directional lines to accomplish high performance reads and writes with minimal additional wiring overhead required. During a read operation, read data is transferred from the memory cells of the device across a series of consecutive pairs of data lines to an input/output port of the memory device. The first pair of data lines is coupled to a data line sense amplifier. The additional pairs of data lines are coupled to additional amplifiers. During a read operation, data is transferred across the consecutive pairs of data lines according to the timing cycles of the respective amplifiers. In order to quickly drive the data signals during a write operation up the series of consecutive pairs of data lines, the timing signals for each of the pairs of data lines except the first pair of data lines are disabled so that the data lines are allowed to float, and then the data lines are overdriven with the write data so that the write data quickly transitions up the series of data lines to the selected data line sense amplifier, where it arrives at approximately the same time that read data normally arrives during the timing cycle for the data line sense amplifier.

REFERENCES:
patent: 5598376 (1997-01-01), Merritt et al.
patent: 5886947 (1999-03-01), Lee

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