High speed synchronous digital data bus system having unterminat

Details High speed synchronous digital data bus system having unterminat High speed synchronous digital data bus system having unterminat

1995-03-27

1998-10-06

Chin, Stephen

Pulse or digital communications

Synchronizers

327141, 370489, H04L 700

Patent

active

058188843

ABSTRACT:
A high speed synchronous digital bidirectional data bus system is provided and includes an M-bit unterminated data bus, an unterminated standing sine wave clock bus, and a plurality of integrated circuit bus interfaces. Each IC bus interface is preferably substantially incorporated on a single CMOS LSI chip and includes M bus drivers with associated send data logic, M data receivers with associated receive data logic, and a clock receiver. The output currents of the bus drivers on all of the chips are preferably stabilized so that each driver drives the bus at substantially the same output current. The drivers are preferably complementary polar driven CMOS logic elements. For this case, for each data receiver, a bus keeper is coupled to the output and the input of the bus receiver to maintain the last state of the data bus. In addition, the clock receivers and the data receivers are embodied as high speed comparators having internal hysteresis. The clock receivers are preferably provided with a delay generator which produces a "guard band" during which the bus drivers are tri-stated before they can drive the data bus. This prevents conflicts on the bus and guarantees end sampling of data.

REFERENCES:
patent: 5255375 (1993-10-01), Crook et al.
patent: 5301186 (1994-04-01), Galuszka et al.
patent: 5355391 (1994-10-01), Horowitz et al.
patent: 5384769 (1995-01-01), Oprescu et al.
patent: 5517532 (1996-05-01), Reymond

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