High speed synchronous/asynchronous local bus and data transfer

Details High speed synchronous/asynchronous local bus and data transfer High speed synchronous/asynchronous local bus and data transfer

1987-01-14

1989-02-21

Eng, David Y.

Boots, shoes, and leggings

G06F 1340

Patent

active

048071099

ABSTRACT:
A high speed local synchronous bus is disclosed for coupling processors within a multi-processor system such that local memory and secondary processing resources may be accessed without impacting data traffic along the bus. The local bus employs a message control method and apparatus which includes the ability to assert a WAIT signal when the processing resource is replying to a request. By asserting the WAIT signal all other operations on the bus are delayed until the transfer is complete. The use of the WAIT signal enables a device operating at a different speed from the primary processing resource to respond across the bus in a manner that is synchronized to the clock speed of the primary processing resource.

REFERENCES:
patent: 3810114 (1974-05-01), Yamada et al.
patent: 4085448 (1978-04-01), Kogge
patent: 4096571 (1978-06-01), Vandermey
patent: 4204208 (1980-05-01), McCarthy
patent: 4281380 (1981-07-01), Demesa
patent: 4390944 (1983-06-01), Quackenbush
patent: 4511960 (1985-04-01), Boudreau

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