Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1998-09-09
2001-05-08
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S199000
Reexamination Certificate
active
06229360
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a synchronization circuit. More particularly, the invention relates to a high speed synchronization circuit in a semiconductor integrated circuit.
2. Description of the Related Art
In a synchronization circuit operative in synchronism with a clock signal, a circuit design based on the clock signal and a D-type flip-flop (DFF) has been currently employed, frequently. There are some synchronization circuit, in which a plurality of circuit structures, each disposing a predetermined logic circuit between DFFs operative in synchronism with the clock signal, are connected in cascade connection. In such case, the DFF serves as a latching circuit which latches an input signal from the logic circuit in the preceding stage in synchronism with the clock signal and feeds the latch signal to the logic circuit in the later stage in synchronism with the clock. Supply of the clock signal to these DFFs is performed by supplying a common clock signal through a clock tree.
An example of a known structure of the DFF to be employed in the synchronization circuit of the type set forth above as the latching circuit is shown in FIG.
7
. In
FIG. 7
, an input signal from an input terminal IN is lead to an output terminal OUT through a transfer gate
73
, an inverter
74
, a transfer gate
77
and an inverter
78
in sequential order . An output of the inverter
74
is fed back to an input of the inverter
74
via an inverter
75
and a transfer gate
76
.
On the other hand, an output of the inverter
78
is fed back to an input of the inverter
78
via an inverter
79
and a transfer gate
80
. A clock signal from a clock input terminal CLK performs ON/OFF control of respective transfer gates
73
,
76
,
77
and
80
.
In the DFF constructed as set forth above, considering a period, in which the input data should not vary before a rise-up timing of the clock signal, namely a set up period T
su
, a period, in which the input data should not vary after rising up of the clock signal, namely a hold period T
hold
, a period, in which an output data varies after rising up of the clock signal, namely a delay period T
pd
, the following definition can be established with reference to FIG.
7
.
The set up period T
su
is defined by a difference between a period required for closing the transfer gate
73
in response to variation of the clock signal and a period, in which an input signal of the input terminal IN varies and the signal reaches a node A
6
. The hold period T
hold
is defined by a period required for closing the transfer gate
73
in response to variation of the clock signal. The delay period T
pd
is defined a period, in which the transfer gate
77
is opened in response to variation of the clock signal and the signal of the node A
4
is propagated to the output terminal OUT.
Now, a minimum value of an input/output delay period required in the logic circuit is considered. Namely, condition that when the clock signal is risen, the output data of the logic circuit receiving the input data upon rising of the immediately preceding clock signal, can be input to the logic circuit in the next stage, is considered. In other words, a condition that upon rising of the clock signal, the output data of the DFF simultaneously does not pass more than one logic circuits to be output data of other DFFs, is considered.
On the other hand, a maximum value of the input/output delay period required in the logic circuit is considered. Namely, a condition that, upon rising of the clock signal, the DFF outputs data, and the output of the DFF passes through the logic circuit to be an output data of the DFF upon rising of the next clock signal, is considered. The input/output delay period to the logic circuit employed in the synchronization circuit includes both of the minimum value and the maximum value.
Assuming that a period of the clock signal is T
cyc
, the maximum value of the input/output delay period of the logic circuit disposed between the DFFs becomes a period subtracted the set up period T
su
, the hold period T
hold
, the delay period T
pd
, a skew of the clock signal and its jitter from the clock period T
cyc
. On the other hand, the minimum value of the input/output delay period of the logic circuit to be disposed between the DFFs is a period subtracted the delay period T
pd
from a sum of the hold period T
hold
and the skew of the clock signal.
For example, in case of a circuit produced by typical 0.35 &mgr;m CMOS process, the set up period T
su
is 150 ps, the hold period T
hold
is 150 ps, the delay period T
pd
is 200 ps, the skew of the clock signal is 150 ps and the jitter thereof is about 150 ps.
Now, when the period T
cyc
of the clock is assumed to be 10 ns (100 MHz), the maximum value of the input/output delay period of the logic circuit to be disposed between the DFFs becomes 9.2 ns, and similarly, the minimum value becomes 100 ps. Similarly, assuming that the period T
cyc
of the clock signal is 1 ns (1 GHz), the maximum value of the input/output delay period of the logic circuit to be disposed between the DFFs becomes 200 ps and, similarly, the minimum value becomes 100 ps.
In general, due to a fluctuation of the diffusion condition of the device, namely due to the fluctuation of the channel length or the oxide layer of the transistor, fluctuation of a temperature or a power source voltage, the input/output delay period of the logic circuit may fluctuate. For example, assuming that the minimum value is one, the maximum value is varied to be about two.
Namely, when the period of the clock signal is assumed to be 1 ns (1 GHz), it becomes quite difficult to set the input/output delay period of the logic circuit between 100 ps to 200 ps. For setting the input/output delay period of the logic circuit between 100 ps to 200 ps, it becomes necessary to use less fluctuation of the diffusion condition of the device by lowering yield in manufacturing and to use temperature control or high precision power source so as not to cause fluctuation of the temperature or the power source voltage, to be a factor of cost-up.
On the other hand, due to timing error of the clock supplied to individual DFF within LSI due to increasing of number of elements or increasing of area of the LSI, the skew of the clock is inherently increased. When the skew of the clock is caused, it becomes difficult to satisfy the hold period of the DFF to cause a necessity to add large number of delay elements between the DFFs to design the circuit for avoiding a signal path having a delay period less than a predetermined minimum delay period. In this case, number of delay elements of the overall LSI becomes huge to cause increasing of the chip area and increasing of power consumption. On the other hand, when the delay element is not added, malfunction of the LSI can be caused.
As a method for solving the foregoing problem, there is a method disclosed in Japanese Unexamined Patent Publication No. Heisei 7-249967, for example.
FIG. 8
shows a construction disclosed in the above-identified publication. In
FIG. 8
, the input signal of the input terminal IN is lead from the output terminal OUT through a transfer gate
88
, an inverter
89
, a transfer gate
90
, an inverter
91
, an inverter
92
, a transfer gate
94
and an inverter
95
in sequential order. On the other hand, an output of the inverter
92
is fed back to an input to the inverter
91
via a transfer gate
93
.
The clock signal CLK is delayed for a given period by an inverter
81
and buffers
82
and
83
and becomes one input of an NAND gate
84
. To the other input of the NAND gate
84
, the clock signal is directly supplied. The output of the NAND gate
84
is used for ON/OFF control of the transfer gates
88
,
90
,
93
and
94
via the inverters
85
,
86
and
87
.
At rising of a pulse signal generated at a node B
3
upon rising of the clock signal, an input data is taken from the input terminal IN. At falling down of the pulse signal, the taken input data is lead to the output ter
Mizuno Masayuki
Yamashina Masakazu
NEC Corporation
Nguyen Linh
Sughrue Mion Zinn Macpeak & Seas, PLLC
Wells Kenneth B.
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