Multiplex communications – Wide area network – Packet switching
Patent
1993-11-18
1995-08-08
Safourek, Benedict V.
Multiplex communications
Wide area network
Packet switching
3408258, H04L 1256
Patent
active
054405505
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a high speed switching architecture, particularly for ATM or fast packet switches.
BACKGROUND ART
The banyan-based architectures are one type of space division packet switching. However, while the banyan-based switches have less crosspoints than other techniques, they do require a means of overcoming blocking, improving throughput and reducing cell loss. This is because of the contention that occurs at a crosspoint when two (or more) inputs want to access the same outlet. These `means` therefore further classify the banyan-based switches into either buffered-banyan or batcher-banyan architectures. The buffered banyan architectures have buffers at the points of contention while the batcher-banyan architectures minimise the contention by sorting the input cells. The buffered banyan architecture has been adopted to realise a switching fabric subsystem. However, these generally involved several levels of buffers at the input, output and intermediate switching stages.
DISCLOSURE OF INVENTION
It is an object of the present invention to provide an architecture which improves the throughput of and minimises the delay through the switching fabric by a packet or ATM cell.
This is achieved by providing a manyfold parallel path internal switch architecture, which requires minimal buffering and multiplexing. According to one aspect the present invention comprises a packet switch, comprising a switching fabric unit (SFU) having a plurality of inputs and a plurality of outputs, each input and output having a respective port controller means, wherein said input port controller means are adapted to convert each input serial packet into a plurality of parallel packets, said SFU including internal parallel paths for each of said plurality of packets, and said output port controller means including means for converting said parallel packets into a serial packet form as input.
The invention will be described with reference to a 16.times.16 switching architecture, i.e., an architecture for switching input ATM cells from 16 inputs and switching to any one of 16 outputs. However, it will be appreciated that the inventive concept is equally applicable to other n.times.n switches.
BRIEF DESCRIPTION OF DRAWINGS
FIG. 1 is a schematic view of one embodiment of a switch according to the present invention;
FIG. 2 is a conceptual view of a format of a packet;
FIG. 3 is an illustration of a switching fabric unit architecture according to one embodiment of the invention;
FIG. 4 illustrates schematically in part one switching fabric architecture;
FIG. 5 illustrates schematically a preferred switching fabric architecture; and
FIG. 6 illustrates the multi-plane switch architecture.
FIG. 7 illustrates the FIFO buffer architecture.
DETAILED DESCRIPTION
Referring to FIG. 1, a schematic block diagram conceptually illustrates a switch 10 comprising a switching fabric with inputs 0-15 and outputs 0-15, i.e. a 16.times.16 switching fabric. The switch also includes input port controllers 30.sub.n on each input 0-15 and output port controllers 20.sub.n on each output 0-15. In a suitable construction input and output port controllers may be the same unit.
Packets to be switched preferably arrive at the input port controller in the form of ATM frames. Referring to FIG. 2, an ATM frame according to an embodiment of the invention comprises a header of at least 3 bytes, and an ATM cell as defined by CCITT recommendation I.361 comprising 53 bytes as payload.
Input port controllers 30.sub.n convert incoming serial ATM frames into an 8 bit wide data stream. The serial ATM frames are converted to parallel packets by sequentially placing received bits onto each parallel link. The output port controllers 20.sub.n perform the reverse operation.
It will therefore be appreciated that links 21.sub.n, 31.sub.n between the SFU and output and input port controllers are in fact each 8-fold parallel connections.
The switching fabric 10 according to the present invention comprises four parallel planes, each pla
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patent: 5109378 (1992-04-01), Proctor et al.
patent: 5303232 (1994-04-01), Proctor et al.
patent: 5317561 (1994-05-01), Fischer et al.
Safourek Benedict V.
Telstra Corporation Limited
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