High speed successive approximation return path and data...

Details High speed successive approximation return path and data... High speed successive approximation return path and data...

2001-07-30

2003-05-06

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000, C341S163000

Reexamination Certificate

active

06559789

ABSTRACT:

FIELD OF INVENTION
The present invention relates in general to switched capacitor circuits and in particular to a high speed successive approximation return path and data conversion methods and circuits using the same
BACKGROUND OF INVENTION
One particular technique for performing analog to digital (A/D) conversion is through successive approximation. The basic successive approximation A/D converter (ADC) includes an analog comparator and a clocked feedback loop having a successive approximation register (SAR) and a digital to analog converter (DAC).
Generally, the analog input signal voltage is sampled onto an array of weighted capacitors, during the sampling phase, the top plates of which are coupled to one comparator input. The other comparator input is coupled to a comparison voltage, which could be a fixed reference voltage in a single-ended system or the voltage at the top plates of second capacitor array in a differential system.
During the first clock cycle of the subsequent conversion phase, the bottom plate of the capacitor representing the digital most significant bit (MSB) is coupled to a reference voltage while the bottom plates of the remaining capacitors in the array are coupled to ground or a second reference voltage (ground will be assumed here). The new top plate voltage appears at the input of the comparator and is compared against the comparison voltage. The new top plate voltage is a scaled version of
[
Voef
2
-
ain
]
·
k
where k is the ratio of capacitors. The sign of this quantity is the factor of interest. If the new top plate voltage is below the comparison voltage, then the MSB is “kept” by the SAR in the feedback loop by maintaining its bottom plate coupled to the reference voltage. On the other hand, if the top plate voltage is above the comparison voltage, the SAR couples and the bottom plate of the MSB capacitor to ground. The state of the MSB capacitor represents the MSB of the digital output word as a Logic 1. The bottom plate of the second MSB is then coupled to the reference voltage and the same test is performed to determine the state of the next digital code bit. The successive approximation algorithm continues by repeating this procedure for the remaining capacitors in the array such that the voltage difference at the inputs to the comparator converge to zero. At the end of this bit cycling process, the configuration of the switches coupling the bottom plates either to Vref or Gnd represents the input sample in digital form.
Successive approximation A/D converters are useful a wide range of applications, including data acquisition, test equipment, instrumentation, cellular communications, among others. Notwithstanding, in order to improve and broaden the utility of this type of A/D converter, significant challenges remain to be addressed. These challenges include improving the device speed given a set of process constraints, reducing the coding error rate, handling metastable states and calibration of the DAC.
SUMMARY OF INVENTION
The present inventive principles are embodied in high speed return paths for use in switched capacitor circuits including an array of capacitors and a plurality of switches for selectively coupling voltages to the capacitors. According to one such embodiment, a set of latches is provided for selectively controlling the plurality of switches during time periods partitioned into non-overlapping reset and set cycles. During the reset cycle, a selected capacitor is decoupled from a current voltage and during the set cycle, the selected capacitor is coupled to a selected reference voltage.
The present inventive concepts are also disclosed in methods for converting bits in charge redistribution analog to digital converters. According to one such method, an input signal is sampled by coupling first and second capacitors to an analog input by setting a first set of latches controlling a first set of switches during a first set cycle. A first bit is then tested during a first conversion period. The first and second capacitors are decoupled from the analog input by resetting the first set of latches controlling the first set of switches. The first capacitor is then coupled to a first reference voltage and the second capacitor to a second reference voltage by setting a second set of latches controlling a second set of switches.
Circuits and methods embodying the principles summarized above have substantial advantages over existing successive approximation return paths. Among other things, the delay introduced into the data conversion process by traditional Break-Before-Make switching logic is substantially reduced or eliminated. At the same time, contention problems which could result if two switches to the same capacitor are closed simultaneously, are advantageously avoided.


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McCreary, Gray “ALL-MOS Charge Redistribution Analog to Digital Conversion Techniques—Part I”, IEEE Journal/Solid-States Circuits, vol., SC10, p. 371-379, Dec. 1975.
Suarez, Gray, & Hodges “All-MOS Charge Redistribution Analog-to-digital Conversion Techniques -Part II” IEEE Journal/Solid State Circuits, vol. SC10, p. 379-385, Dec. 1975.

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