High speed strobed comparator circuit having a latch circuit

Details High speed strobed comparator circuit having a latch circuit High speed strobed comparator circuit having a latch circuit

1997-09-19

2000-05-09

Tran, Toan

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

327 55, 327 65, 327215, G11C 706, H03K 3356

Patent

active

060609125

ABSTRACT:
A strobed comparator circuit with reduced signal propagation time has a regenerative latch in which, during the reset phase of operation, its output nodes are discharged to a common potential which is close to the regenerative voltage level of the cross-coupled transistors forming such regenerative latch rather than to circuit ground. Accordingly, overall signal propagation time is reduced by the amount of reduction in charging time necessary for one of the discharged nodes to recharge above the threshold voltage of one of the cross-coupled latch transistors. Also included is an output monitoring circuit which determines whether the regenerative latch has remained in a metastable state.

REFERENCES:
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patent: 5528178 (1996-06-01), Pelella
patent: 5537066 (1996-07-01), Kawashima
Behzad Razavi and Bruce A. Wooley, "Design Techniques for High-Speed, High-Resolution Comparators", IEEE Journal of Solid-State Circuits, vol. 27, No. 12, Dec. 1992, pp. 1916-1926.
H.L. Fiedler and B. Hoefflinger, "A CMOS Pulse Density Modulator for High-Resolution A/D Converters", IEEE Journal of Solid-State Circuits, vol. SC-19, No. 6, Dec. 1984, pp. 995-996.

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