High speed static random access memory circuit

Details High speed static random access memory circuit High speed static random access memory circuit

1988-06-16

1990-08-07

Hecker, Stuart N.

Static information storage and retrieval

Addressing

Sync/clocking

365227, G11C 700

Patent

active

049473794

ABSTRACT:
A static random access memory (RAM) circuit arranged such that the data stored in a memory cell is readout by detecting a transition address signal level. That is, an address transition pulse is generated by detecting an address signal transition, and first and second pulses are generated by detecting a starting edge and a trailing edge of the address transition pulse respectively. The first pulse enables a selected word line for reading out the data stored in selected memory cells. The second pulse enables an data output circuit coupled to the bit lines for transferring the readout data to an output terminal. Under such an arrangement, memory access operation becomes faster, and even if "skew" phenomenon is caused, the transient data readout from the memory cells instantaneously is prevented from being transferred to the output terminal.

REFERENCES:
patent: 4641044 (1987-02-01), Shiraishi
patent: 4701889 (1987-10-01), Ando
patent: 4707809 (1987-11-01), Ando
patent: 4712194 (1987-12-01), Yamaguchi et al.
patent: 4728820 (1988-03-01), Lee

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