High speed static latch

Details High speed static latch High speed static latch

2000-07-28

2002-02-19

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S208000, C327S218000

Reexamination Certificate

active

06348824

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to high speed data latches. More specifically the invention relates to a high speed data latch having a reduced delay time.
BACKGROUND
Latches are well known in the art and are often used for buffering or temporarily storing data in computer systems. A standard static latch uses a single data path having a transmission gate, a feedback structure and an output driver. The transmission gate is coupled to receive data and a clock signal CLK. The transmission gate will allow the data pass through the gate and into the latch when the clock signal CLK is active. As the data passes through the transmission gate, the feedback structure is first loaded with the data as it passes through the single data path. The data is then passed through an output driver, where it drives an output Q from the latch. When the clock signal CLK is inactive, the data stored in the feedback structure continues to pass through the output driver and drive the output Q from the latch. This feedback structure prevents any feedback through the driver from corrupting the data in the latch and leading to an erroneous output while the clock signal CLK is inactive.
FIG. 1
illustrates a conventional static latch structure
101
. As shown, the conventional static latch
101
consists of a single data path having a transmission gate
105
, a feedback structure
110
, and an output driver
115
. In
FIG. 1
, the output driver
115
illustrated is a non-inverting output driver, although it is understood that the output driver may be either inverting or non-inverting. The transmission gate
105
is coupled to receive data at the input D. The transmission gate
105
is also coupled to receive a clock signal CLK and an inverted version of the clock signal {overscore (CLK)}. When the clock signal CLK is active and the inverted clock signal {overscore (CLK)} is inactive, the transmission gate
105
operates in a forward flow mode and data passes from the input D through the gate
105
.
The conventional static latch
101
also includes a feedback structure
110
, comprised of two inverters
111
and
112
arranged in a loop. As data passes through the transmission gate
105
, it flows along the first data path and is loaded into the feedback structure
110
. The feedback structure
110
stores data in the latch until the next time the clock signal CLK is active and prevents any feedback though the driver
115
from invalidating the data in the latch, thereby preventing errors at the output. Finally, the data is inverted and passed through the output driver
115
, where it is amplified for driving a voltage at the output Q toward a logic high or logic low voltage level.
One major drawback to this structure is delay. The use of a single data path requires that the feedback structure
110
be loaded with the data before it is provided to the output driver
115
, for driving the output node. The delay required to load the feedback structure
110
slows the propagation of data through the static latch
101
. What is needed is a latch design which performs more quickly and does not include the significant delays inherent in the prior art.
SUMMARY OF THE INVENTION
The present invention is for a new static latch structure which has a significantly reduced delay time. In a first aspect, the new static latch includes two individual data paths. A first data path is used for passing the data to an output driver for driving a voltage level at the output from the latch toward a logic high or logic low voltage level depending upon the data. A second data path is used for storing the data in a feedback structure so the latch can continue to drive the voltage level at the output node until the next data is loaded into the latch.
In a further aspect, the conventional output driver found in prior art static latches is replaced with a tri-state driver. The tri-state driver allows the data stored in the feedback structure to continue to drive the voltage level at the output node while preventing feedback from corrupting data stored in the latch. The use of a tri-state driver eliminates that need for a feedback structure in the first data path because the data cannot be corrupted by feedback through the tri-state driver and into the first data path since there is no flow from the source to the gate of the tri-state driver.
By moving the feedback structure into a separate data path, a much faster static latch can be implemented that is useful in circuits where local latching is required. In fact, by moving the feedback structure into a second data path, up to 75% of the delays associated with traditional static latches is eliminated.


REFERENCES:
patent: 6107852 (2000-08-01), Durham et al.
patent: 6211713 (2001-04-01), Uhlmann
patent: 6239640 (2001-05-01), Liao et al.

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