High-speed staged decoder/quantizer

Details High-speed staged decoder/quantizer High-speed staged decoder/quantizer

1994-05-20

1996-01-23

Gordon, Paul P.

Excavating

371 43, 341200, G06F 1110, H03M 1300

Patent

active

054870755

ABSTRACT:
A symbol-level pipelined structure for parallel systolic decoding of block codes which is a layered processor structure including a number of layers equal to the code length and each layer is adapted to decode the component codes of a concatenated code in sequence. The structure described provides efficient high rate decoding operation with an associated low cost and low hardware complexity.

REFERENCES:
patent: 5329536 (1994-07-01), Darmon et al.
G. David Forney, Jr., "The Dynamics of Group Codes: State Spaces, Trellis Diagrams and Canonical Encoder" IEEE Transactions on Information Theory, vol. 39, No. 9, Sep. 1993.
G. Fettweis, H. Meyr, "High-Rate Viterbi Processor: a Systolic Array Solution", IEEE Journal on Selected Areas in Communications, vol. 8, No. 8, Oct. 1990.
E. Biglieri, A Spalvieri: Generalized Concatenation: A Tutorial, Elsevier, 1992.
G. Claire, J. Ventura, J. Murphy, S. Y. Kung, "VLSI Systolic Array Implementation of a Staged Decoder for BCM Signals", Proceedings of the IEEE workshop on VLSI signal processing, Napa, Calif., USA, Oct. 28-30, 1992.
E. Biglieri, "Parallel Demondulation of Multi-dimensional Signals", IEEE Trans. on Commun., vol. 40, No. 10, Oct. 1992.

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