Electrical connectors – Preformed panel circuit arrangement – e.g. – pcb – icm – dip,... – With provision to conduct electricity from panel circuit to...
Patent
1998-07-29
2000-08-29
Abrams, Neil
Electrical connectors
Preformed panel circuit arrangement, e.g., pcb, icm, dip,...
With provision to conduct electricity from panel circuit to...
361790, H01R 1200, H05K 100
Patent
active
061099295
ABSTRACT:
A stackable memory system for minimizing the stub lengths of the memory data bus and data skew. The invention provides a memory controller, a memory connector, a data bus, a first stackable memory module and a terminator plate. The data bus electrically connects the controller to the memory connector. The first stackable memory module is mechanically and electrically connected to the memory connector. The terminator plate is adapted to substantially reduce reflections to the data bus and is electrically connected to the data bus through the first stackable memory module. Additional, the memory system may be expanded by adding stackable memory modules substantially similar to the first stackable memory module to the stackable memory system between the first memory module and the terminator plate. Each stackable memory module may include memory chips each of which has trace lines connecting the memory chip to a module connector. Each of the trace lines is substantially equal in length and connects to a single side of the memory chip.
REFERENCES:
patent: 4739473 (1988-04-01), Ng et al.
patent: 4761730 (1988-08-01), Ng et al.
patent: 4909746 (1990-03-01), Scholz
patent: 5128831 (1992-07-01), Fox, III et al.
patent: 5176526 (1993-01-01), Hillbish et al.
patent: 5181855 (1993-01-01), Mosquera et al.
patent: 5229960 (1993-07-01), De Givry
patent: 5497471 (1996-03-01), Gillett
patent: 5544017 (1996-08-01), Beilin et al.
patent: 5583749 (1996-12-01), Tredennick et al.
patent: 5636997 (1997-06-01), Kuroda et al.
patent: 5652462 (1997-07-01), Matsunaga et al.
patent: 5707242 (1998-01-01), Mitra et al.
patent: 5742097 (1998-04-01), Matsunaga et al.
patent: 5884319 (1999-03-01), Hafner et al.
patent: 5963464 (1999-10-01), Dell et al.
patent: 6049467 (2000-04-01), Tamarkin et al.
Abrams Neil
Agilent Technologie,s Inc.
Hyeon Hae Moon
LandOfFree
High speed stackable memory system and device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High speed stackable memory system and device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed stackable memory system and device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1242987