Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By shape
Reexamination Certificate
2007-03-13
2007-03-13
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By shape
C327S041000, C327S141000, C327S077000
Reexamination Certificate
active
11176439
ABSTRACT:
A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and /SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against /SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using exclusive-OR logic with SSVTR and /SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and /SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is de-coupled if no transition occurs.
REFERENCES:
patent: 3678399 (1972-07-01), Mottier et al.
patent: 3737788 (1973-06-01), Lenz
patent: 4247817 (1981-01-01), Heller
patent: 4404526 (1983-09-01), Kirn
patent: 4675558 (1987-06-01), Serrone et al.
patent: 4713827 (1987-12-01), Lauffer et al.
patent: 4745365 (1988-05-01), Ugenti
patent: 4782481 (1988-11-01), Eaton
patent: 4792845 (1988-12-01), Judge
patent: 4942365 (1990-07-01), Satterwhite
patent: 5023488 (1991-06-01), Gunning
patent: 5105107 (1992-04-01), Wilcox
patent: 5142556 (1992-08-01), Ito
patent: 5243703 (1993-09-01), Farmwald et al.
patent: 5254883 (1993-10-01), Horowitz et al.
patent: 5263049 (1993-11-01), Wincn
patent: 5319755 (1994-06-01), Farmwald et al.
patent: 5327121 (1994-07-01), Antles, II
patent: 5355391 (1994-10-01), Horowitz et al.
patent: 5363100 (1994-11-01), Bailey et al.
patent: 5363332 (1994-11-01), Murabayashi et al.
patent: 5408129 (1995-04-01), Farmwald et al.
patent: 5432823 (1995-07-01), Gasbarro et al.
patent: 5463211 (1995-10-01), Arends et al.
patent: 5473575 (1995-12-01), Farmwald et al.
patent: 5473635 (1995-12-01), Chevroulet
patent: 5473757 (1995-12-01), Sexton
patent: 5479337 (1995-12-01), Voigt
patent: 5483110 (1996-01-01), Koide et al.
patent: 5512853 (1996-04-01), Ueno et al.
patent: 5513327 (1996-04-01), Farmwald et al.
patent: 5513377 (1996-04-01), Capowski et al.
patent: 5550496 (1996-08-01), Desroches
patent: 5579492 (1996-11-01), Gay
patent: 5590369 (1996-12-01), Burgess et al.
patent: 5606717 (1997-02-01), Farmwald et al.
patent: 5646642 (1997-07-01), Maekawa et al.
patent: 5706484 (1998-01-01), Mozdzen et al.
patent: 5706485 (1998-01-01), Barkatullah et al.
patent: 5715405 (1998-02-01), McClear et al.
patent: 5774354 (1998-06-01), Ohta
patent: 5796962 (1998-08-01), Fant et al.
patent: 5812875 (1998-09-01), Eneboe
patent: 5815734 (1998-09-01), Lee et al.
patent: 5878234 (1999-03-01), Dutkiewicz et al.
patent: 5925118 (1999-07-01), Revilla et al.
patent: 5928343 (1999-07-01), Farmwald et al.
patent: 5945850 (1999-08-01), Segan et al.
patent: 5963070 (1999-10-01), Faulkner et al.
patent: 6122331 (2000-09-01), Dumas
patent: 6160423 (2000-12-01), Haq
patent: 6255859 (2001-07-01), Haq
patent: WO92/17938 (1992-10-01), None
“IEEE Standard for Low-Voltage Differential Signals (LVDS) for Scalable Coherent Interface (SCI),” IEEE Std. 1596.3-1996, Mar. 21, 1996, XP-002106653, Introduction, Contents and pp. 1-30.
4M =SLDRAM Preliminary Data Sheet Sep. 1997 from SLDRAM Consortium.
1M=16Bit=4 Banks DDR SDRAM (Rev. 0.5 Jun. 1997) from Samsung.
Kim et al., “A 640MB/s Bi-Directional Data Strobed, Double-Data-Rate SDRAM with a 40mW DLL Circuit for a 256MB Memory System,” ISSCC98 Digest, pp. 158-159, Feb. 8, 1998.
Morooka et al., “Source Synchronization and Timing Vernier Techniques for 1.2GB/s SLDRAM Interface,” ISSCC98 Digest, pp. 160-161, Feb. 6, 1998.
Lau et al., “A 2.6 GB/s Multi-Purpose Chip-to-Chip Interface,” ISSCC98 Digest, pp. 162-163, Feb. 6, 1998.
LVDS I/O (Scalable Coherent Interface Documents) IEEE P1596.3 working-group activity for high-speed signal link interface, 3 pages.
Hyper-LVDS I/O Cells (LSI Logic Product Briefs), 2 pages.
Richard Crisp, “Direct Rambus Technology: The New Main Memory Standard,” Nov./Dec. 1997 issue of IEEE Micro.
Direct RDRAM 64/72-Mbit (256Kx16/18=16d), “Advance Information” of 64M/72M Direct RDRAM Data Sheet, dated Oct. 2, 1997.
Tamura et al., “PRD-Based Global-Mean-Time Signalling for High-Speed Chip-to-Chip Communications,” ISSCC98 Digest, pp. 164-165 & pp. 430-432, Feb. 6, 1998.
Griffin et al., “A Process Independent 800MB/s DRAM Bytewide Interface Featuring Command Interleaving and Concurrent Memory Operation,” ISSCC98 Digest, pp. 156-157, Feb. 6, 1998.
RamLink, LVDS I/O (Scalable Coherent Interface Documents) IEEE P1596.4 working-group activity for high-speed signal link interface, 3 pages.
XILINX® Application Note: “Using the Virtex SelectIO,” XAPP 133 Oct. 21, 1998 (Version 1.11), 12 pages.
Rambus®, Rambus® Technology Overview, including Introduction and The Rambus Solution, Copyright Feb. 1999, last modified: Feb. 12, 1999, 5 pages.
Schumacher et al., “CMOS Subnanosecond True-ECL Output Buffer,” IEEE Journal of Solid-State Circuits, Feb. 1990, pp. 150-154, vol. 25, No. 1, IEEE.
Jazio, Inc.
Thelen Reid Brown Raysman & Steiner LLP
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