Television – Camera – system and detail – Solid-state image sensor
Reexamination Certificate
1999-06-01
2004-10-05
Garber, Wendy R. (Department: 2612)
Television
Camera, system and detail
Solid-state image sensor
C348S300000, C348S301000, C348S302000
Reexamination Certificate
active
06801256
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a solid-state imaging device, and more particularly to a circuit for suppressing leakage current at the signal storage nodes of a CMOS solid-state image sensor (CMOS image sensor) with a read circuit capable of reading an image signal pixel by pixel, a circuit of suppressing the current drawn by an image signal amplifying source follower, and a horizontal readout gate providing a horizontal signal line with less parasitic capacitance, which are used in, for example, a video camera or an electronic still camera.
FIG. 20
shows an equivalent circuit of a conventional CMOS solid-state image sensor (amplification CMOS image sensor) (conventional equivalent 1) with a read circuit capable of reading an image signal pixel by pixel.
In the sensor of
FIG. 20
, a cell area (imaging area)
1
is composed of plural unit cells
13
arranged in a two-dimensional matrix. One unit cell corresponds to one pixel.
Each unit cell
13
is composed of, for example, four transistors and one photodiode. Specifically, each unit cell
13
includes a photodiode
8
to whose anode the ground potential is applied, a read transistor (shutter gate transistor)
14
one end of which is connected to the cathode of the photodiode
8
, an amplifying transistor
15
whose gate is connected to the other end of the read transistor
14
, a vertical select transistor
16
one end of which is connected to one end of the amplifying transistor
15
, and a reset transistor
17
one end of which is connected to the gate of the amplifying transistor
15
. In the cell area
1
, the following lines are formed: read lines connected in common to the gates of the individual read transistors of the unit cells in the same rows, vertical select lines
6
connected in common to the gates of the individual read transistors
14
of the unit cells in the same rows, reset lines
7
connected in common to the gates of the individual reset transistors of the unit cells in the same rows, vertical signal lines
18
-i (i=1 to n) connected in common to the other end of the individual amplifying transistors
15
of the unit cells in the same columns, and power lines
9
connected in common to the other end of the individual reset transistors and to the other end of the individual vertical select transistors
16
of the unit cells in the same columns.
Outside the cell area
1
, the following component parts are provided: load transistors
12
connected between one end of the respective vertical signal lines
18
-i and the ground nodes, horizontal select transistors
23
-i one end of which is connected to the other end of the respective vertical signal lines
18
-i via the corresponding noise chancellor circuits
25
-i, a horizontal signal line
26
connected in common to the other end of the horizontal select transistors
23
-i, an output amplifier circuit
27
connected to the horizontal signal line
26
, a horizontal reset transistor
28
connected to the horizontal signal line
26
, a vertical shift register
2
for supplying a select signal in a scanning manner to the vertical select lines
6
of each row in the cell area
1
and driving the vertical select transistors
16
in each row in a scanning manner, a horizontal register
3
for driving the horizontal select transistors
23
-i in a scanning manner, and a timing generator circuit
10
for generating various timing signals.
Each of the noise chancellor circuits
25
-i is composed of, for example, two transistors and two capacitors. Specifically, each noise chancellor circuit is composed of a sample hold transistor
19
one end of which is connected to the other end of the vertical signal line
18
-i, a coupling capacitor
20
one end of which is connected to the other end of the sample hold transistor
19
, a charge accumulation capacitor
21
connected between the other end of the coupling capacitor
20
and the ground node, and a potential clamping transistor
22
connected to the junction node of the capacitors
20
,
21
. One end of the corresponding one of the horizontal select transistors
23
-i is connected to the junction node of the capacitors
20
,
21
.
Each of the horizontal select transistors
23
-i is made up of an NMOS transistor having an active region (SDG region) formed in a p-well selectively formed at the surface of a semiconductor substrate. The p-well is connected to the ground potential.
FIG. 21
is a timing waveform diagram to help explain the operation of the solid-state image sensor of FIG.
20
. Referring to
FIG. 21
, the operation of the solid-state image sensor of
FIG. 20
will be explained.
The incident light on each photodiode
8
is converted photoelectrically and the resulting signal charges are accumulated in the photodiodes
8
.
Before the operation of reading the signal charge, a high reset signal is applied to the reset line
7
for a specific period of time to reset the gate potential of the amplifying transistor
15
. The reset transistor
17
is on for the specific period, resetting the gate potential of the amplifying transistor
15
to a desired potential.
At the same time, a high select signal is supplied to the vertical select line (address line)
6
selected in a scanning manner by the vertical shift transistor
2
. The select signal from the vertical select line
6
turns on the vertical select transistor
16
. The power supply line
9
supplies a voltage to the amplifying transistor
15
via the vertical select transistor
16
. This causes the source-follower-connected amplifying transistor
15
to output a potential proportional to its gate potential to the corresponding vertical signal line
18
-i.
There is a variation in the gate potential of the reset amplifying transistor
15
. As a result, a variation appears in the reset potential of the vertical signal line
18
-i connected to the drain of the amplifying transistor
15
.
To reset the variation in the reset potential of each vertical signal line
18
-i, the sample hold transistor
19
is turned on after the reset transistor
17
has been turned on. As a result, the reset potential of the vertical signal line
18
-i is transmitted to the capacitor
21
via the capacitor
20
. Thereafter, the potential clamping transistor
22
is kept on for a specific period, fixing the voltage of the junction node of the capacitors
20
,
21
at a constant level.
Next, the read line
4
corresponding to the desired row is selected (or supplied with a high read signal), turning on the read transistor
14
. This causes the accumulated charge in the photodiode
8
to be transferred to the gate of the amplifying transistor
15
via the read transistor
14
, which changes the gate potential. The amplifying transistor
15
outputs a voltage signal proportional to the amount of change of the gate potential to the corresponding vertical signal line
18
-i.
As a result, the change in the voltage signal on the vertical signal line
18
-i caused by the read operation after resetting has been transferred to the capacitor
21
via the capacitor
20
. This removes the noise introduced in the stages before the noise chancellor circuit
25
-i, such as variations in the reset potential of each vertical signal line
18
-i occurring in the cell area
1
.
After the noise removing operations have been carried out, the sample hold transistor
19
is turned off and the vertical select transistor
16
is also turned off. As a result, the unit cell
13
is brought into the unselected state and the cell area
1
is electrically disconnected from each noise chancellor circuit
25
-i.
Then, the horizontal reset transistor
28
is turned on, which resets the horizontal signal line
26
. Thereafter, the horizontal select transistors
23
-i are turned on sequentially, causing the voltages at the junction nodes (signal storage nodes SN) of the capacitors
20
,
21
to be read sequentially. The read-out voltages are amplified by the output amplifier circuit
27
, which then outputs the amplified voltages.
The above-described noise removing operations are carried out
Egawa Yoshitaka
Endo Yukio
Kusakabe Hiromi
Ohsawa Shinji
Tanaka Nagataka
Garber Wendy R.
Kabushiki Kaisha Toshiba
Nguyen Luong
LandOfFree
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