Data processing: structural design – modeling – simulation – and em – Emulation – In-circuit emulator
Reexamination Certificate
2006-09-12
2006-09-12
Rodriguez, Paul L. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Emulation
In-circuit emulator
Reexamination Certificate
active
07107203
ABSTRACT:
A system and method for determining which of several possible cable lengths has been used by reversing the end-to-end correspondence of at least two conductors in the cable. A different two conductors are selected to identify respective different cable lengths. Each input pin is connected to a correspondingly identified output pin, except for the pair with the outputs reversed, which pair signifies the cable length.
REFERENCES:
patent: 3903380 (1975-09-01), Schomburg
patent: 4100721 (1978-07-01), Seiichi et al.
patent: 4104582 (1978-08-01), Lambertsen
patent: 4380931 (1983-04-01), Frost et al.
patent: 4797604 (1989-01-01), Rocci et al.
patent: 5157665 (1992-10-01), Fakhraie-Fard et al.
patent: 5226047 (1993-07-01), Catlin
patent: 5352123 (1994-10-01), Sample et al.
patent: 5452231 (1995-09-01), Butts et al.
patent: 5551013 (1996-08-01), Beausoleil et al.
patent: 5644515 (1997-07-01), Sample et al.
patent: 5784600 (1998-07-01), Doreswamy et al.
patent: 5903744 (1999-05-01), Tseng et al.
patent: 5951704 (1999-09-01), Sauer et al.
patent: 5963735 (1999-10-01), Sample et al.
patent: 6122443 (2000-09-01), Nishikawa
patent: 6421251 (2002-07-01), Lin
patent: 6504841 (2003-01-01), Larson et al.
patent: 6618698 (2003-09-01), Beausoleil et al.
patent: 6694464 (2004-02-01), Quayle et al.
Mak et al. Board-Level Multi-terminal Net Routing for FPGA-based Logic Emulation. 1997 ACM p. 152-167.
Donath-W.E., Placement and Average Interconnection Lengths of Computer Logic 1979. IEEE p. 272-276.
IBM. “Machine Organization and Rent's Rule” 1999. p. 1-6.
U.S. Appl. No. 09/656,147, filed Sep. 6, 2000; Entitled: High Speed Software Driven Emulator Comprised Of A Plurality Of Emulation Processors With An Improved Maintenance Bus That Streams Data At High Speed; W.F. Beausoleil, et al.
U.S. Appl. No. 09/656,541, filed Sep. 6, 2000; Entitled: High Speed Software Driven Emulator Comprised Of A Plurality Of Emulation Processors With A Method To High Speed Bulk Read/Writes Operation Synchronous Dram While Refreshing The Memory; W.F. Beausoleil, et al.
U.S. Appl. No. 09/596,596, filed Sep. 6, 2000; Entitled: High Speed Software Driven Emulator Comprised Of A Plurality Of Emulation Processors With A Method To Allow Memory Read/Writes Without Interrupting The Emulation; W.F. Beausoleil, et al.
U.S. Appl. No. 09/656,146, filed Sep. 6, 2000; Entitled: High Speed Software Driven Emulator Comprised Of A Plurality Of Emulation Processors With Improved Multiplexed Data Memory; W.F. Beausoleil, et al.
Beausoleil William F.
Cook R. Bryan
Ng Tak-kwong
Roth Helmut
Tannenbaum Peter
Orrick Herrington & Sutcliffe LLP
Quickturn Design Systems Inc.
Rodriguez Paul L.
Stevens Tom
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