Data processing: structural design – modeling – simulation – and em – Emulation – Of peripheral device
Reexamination Certificate
2005-05-31
2005-05-31
Teska, Kevin J. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Emulation
Of peripheral device
C703S023000, C703S028000, C712S010000, C712S011000, C711S147000, C711S151000
Reexamination Certificate
active
06901359
ABSTRACT:
A system and method for bulk transfer to and from the SRAMs in which a starting memory address is latched and is then incremented every clock cycle to generate a new memory address. The addresses are decoded and memory requests are pipelined to the SRAM memory, one every clock cycle. When the memory controller detects transfer of the boundary of a predetermined number of clock cycles or words (e.g. 64 words or four clock cycles) the burst mode of data transfer is stopped and the memory controller waits for a “done” signal before resuming another cycle of the burst transfer mode. The memory controller on detecting a request on this address boundary first does a memory refresh followed by a requested operation; e.g. a continuation of the transfer operation.
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Beausoleil William F.
Cook R. Bryan
Ng Tak-kwong
Roth Helmut
Tannenbaum Peter
Orrick Herrington & Sutcliffe LLP
Quickturn Design Systems Inc.
Sharon Ayal
Teska Kevin J.
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