High speed single phase to dual phase clock divider

Details High speed single phase to dual phase clock divider High speed single phase to dual phase clock divider

1995-12-22

2001-06-12

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S233000, C327S257000, C327S259000

Reexamination Certificate

active

06246278

ABSTRACT:

TECHNICAL FIELD
The present invention relates to electrical circuitry, and more particularly to a clock circuit for use in high speed applications.
BACKGROUND OF THE INVENTION
In high speed circuits, complementary clocking signals are often used to improve the performance of clocked elements (i.e. flip-flops, latches, etc.). Prior approaches to generating complementary clocks used two dividers with the output of the first being inverted and fed into the input of the second. This approach is performance limited by the fact that sufficient setup time is required into the second stage divider before another clock pulse can be received.
At very high speeds, clock skew between complementary clock signals becomes a significant performance issue in clocked elements.
It is an object of the present invention to provide a means for generating high speed complementary clock signals from a single clock input.
It is another object of the present invention to provide a circuit that uses dynamic clocked elements.
It is yet another object of the present invention to provide a clock recovery circuit that eliminates an inverted feedback path.
SUMMARY OF THE INVENTION
A dual-phase clock divider circuit provides the ability to generate high speed complementary clocks with low skew. The dual-phase clock divider circuit runs off a single clock input, such as provided by a high speed VCO. This eliminates the effect of clock skew in the highest speed portion of the circuit. The dual-phase clock divider then generates complementary outputs of low skew to be used by other clocked elements.
The invention achieves the above stated objectives by eliminating the traditional approach of inverted feedback paths and clumsy signal splitting methods. The operational speed of the circuit is therefore limited mainly by the technology used to implement the design, rather than the specific circuit structure in prior approaches. This invention has wide usage applicability in high speed circuitry where setup/hold times and clock skew are of major concern.


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