High speed single chip digital video network apparatus

Details High speed single chip digital video network apparatus High speed single chip digital video network apparatus

1994-12-08

1999-01-05

Hsu, Alpus H.

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

370402, 370466, 370474, 348 7, 348467, 3488452, 364514C, H04L 1256, H04N 704

Patent

active

058569758

ABSTRACT:
A high speed digital video network apparatus is implemented on a single integrated circuit chip, and includes a network protocol processing system interconnection, compression/decompression circuits, and encoder/decoder circuits. The interconnection includes a packet conversion logic which converts between a network protocol, such as Asynchronous Transfer Mode (ATM) packets, and the data protocol used to handle large data streams, such as Motion Picture Experts Group (MPEG) packets. The interconnection further includes a Virtual Channel Memory (VCM) for storing ATM cells for segmentation and reassembly, a Direct Memory Access (DMA) controller for connecting the VCR to the compression/decompression circuits, a Parallel Cell Interface (PCI) for connecting the VCM to an ATM network, a Pacing Rate Unit (PCU) for automatically reducing the maximum transmission rate in response to a sensed congestion condition in the network, and a Reduced Instruction Set Computer (RISC) microprocessor for controlling the DMA controller and transfers between the memory, a host and the ATM network, for performing segmentation and reassembly of Conversion Sublayer Payload Data Units (CD-PDUs), and for performing conversion between the ATM Protocol and the MPEG protocol. The compression/decompression and decoder/encoder circuits may utilize MPEG to compress digitized images and motion video into compact data streams that can be moved across networks with bandwidths too narrow to accommodate the uncompressed data. The operating program for the RISC microprocessor is stored in a volatile Instruction Random Access Memory (IRAM) in the form of firmware which can be downloaded at initialization.

REFERENCES:
patent: 4710916 (1987-12-01), Amstutz et al.
patent: 4803485 (1989-02-01), Rypinski
patent: 4831620 (1989-05-01), Conway et al.
patent: 4907225 (1990-03-01), Gulick et al.
patent: 4939724 (1990-07-01), Ebersole
patent: 4947388 (1990-08-01), Kuwahara et al.
patent: 4956839 (1990-09-01), Torii et al.
patent: 4969147 (1990-11-01), Markkula, Jr. et al.
patent: 5018138 (1991-05-01), Twitty et al.
patent: 5058110 (1991-10-01), Beach et al.
patent: 5062106 (1991-10-01), Yamazaki et al.
patent: 5072440 (1991-12-01), Isono et al.
patent: 5072442 (1991-12-01), Todd
patent: 5079762 (1992-01-01), Tanabe
patent: 5079764 (1992-01-01), Orita et al.
patent: 5086426 (1992-02-01), Tsukakoshi et al.
patent: 5088090 (1992-02-01), Yacoby
patent: 5088091 (1992-02-01), Schroeder et al.
patent: 5105424 (1992-04-01), Flaig et al.
patent: 5119370 (1992-06-01), Terry
patent: 5121390 (1992-06-01), Farrell et al.
patent: 5130975 (1992-07-01), Akata
patent: 5130977 (1992-07-01), May et al.
patent: 5130981 (1992-07-01), Murphy
patent: 5130984 (1992-07-01), Cisneros
patent: 5140583 (1992-08-01), May et al.
patent: 5144622 (1992-09-01), Takiyasu et al.
patent: 5151935 (1992-09-01), Slife et al.
patent: 5153920 (1992-10-01), Danner
patent: 5157662 (1992-10-01), Tadamura et al.
patent: 5163047 (1992-11-01), Perdikaris et al.
patent: 5166926 (1992-11-01), Cisneros et al.
patent: 5173897 (1992-12-01), Schrodi et al.
patent: 5175732 (1992-12-01), Hendel et al.
patent: 5179555 (1993-01-01), Videlock et al.
patent: 5179558 (1993-01-01), Thacker et al.
patent: 5189666 (1993-02-01), Kagawa
patent: 5189668 (1993-02-01), Takatori et al.
patent: 5204857 (1993-04-01), Obara
patent: 5210748 (1993-05-01), Onishi
patent: 5214642 (1993-05-01), Kunimoto et al.
patent: 5214646 (1993-05-01), Yacoby
patent: 5214650 (1993-05-01), Renner et al.
patent: 5216669 (1993-06-01), Hofstetter et al.
patent: 5218680 (1993-06-01), Farrell et al.
patent: 5220563 (1993-06-01), Grenot et al.
patent: 5222085 (1993-06-01), Newman
patent: 5226120 (1993-07-01), Brown et al.
patent: 5229991 (1993-07-01), Turner
patent: 5229994 (1993-07-01), Balzano et al.
patent: 5239542 (1993-08-01), Breidenstein et al.
patent: 5241682 (1993-08-01), Bryant et al.
patent: 5245606 (1993-09-01), DeSouza
patent: 5247516 (1993-09-01), Bernstein et al.
patent: 5260783 (1993-11-01), Dixit
patent: 5280474 (1994-01-01), Nickolls et al.
patent: 5280476 (1994-01-01), Kojima et al.
patent: 5340978 (1994-08-01), Rostoker et al.
patent: 5396497 (1995-03-01), Veltman
patent: 5448568 (1995-09-01), Delpuch et al.
patent: 5467342 (1995-11-01), Logston et al.
patent: 5481543 (1996-01-01), Veltman
patent: 5544161 (1996-08-01), Bigham et al.

Affiliated with

Also associated with

Rating

High speed single chip digital video network apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High speed single chip digital video network apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed single chip digital video network apparatus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-867279