High speed silicon-on-insulator device

Details High speed silicon-on-insulator device High speed silicon-on-insulator device

1991-01-28

1992-08-18

James, Andrew J.

357 4, 357 42, 357 59, H01L 2701

Patent

active

051403900

ABSTRACT:
High speed silicon-on-insulator radiation hardened semiconductor devices and a method of fabricating same. Starting with a SIMOX wafer (10) having a layer of silicon (12) on a layer of buried oxide (11), P-well and N-well masks are aligned to an oversized polysilicon mask (16). This produces relatively thick source and drain regions (18) and relatively thin gate regions (17). The relatively thick source and drain regions (18) educe the risk of dry contact etch problems. N-channel and P-channel threshold voltages are adjusted prior to the formation of active areas, thus substantially eliminating edge and back channel leakage. A sacrificial thin oxide layer (21) is employed in fabricating the N-well and P-well implants so that both front and back channel threshold voltage adjustments are controlled. Good control of doping profiles is obtained, leading to excellent threshold voltage control and low edge and back channel leakages. The speed of devices fabricated using the method of the present invention is high due to reduced capacitances resulting from thinner silicon-on-insulator films. The present invention is fabricated using present equipment and available technology, and provides an easy, straight forward and cost-effective process to fabricate very high speed CMOS devices which are latch-up free and radiation hardened.

REFERENCES:
patent: 4679062 (1987-07-01), Okamoto
patent: 4835597 (1989-05-01), Okuyama et al.
patent: 4907048 (1990-03-01), Huang
patent: 4948231 (1990-08-01), Aoki et al.
patent: 4992846 (1991-02-01), Sakakibara et al.
patent: 4999690 (1991-03-01), Rodder

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