High speed signal processor

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Details

364726, G06F 738

Patent

active

048232955

ABSTRACT:
A high speed signal processor contains a set of repetitive architecture functional units including an input data storage unit for storing quantized data values, a data shifting unit, an output data accumulator and a control code generator. The data shifting unit is coupled in parallel to each of a plurality of controllable data accumulator sections of the output data accumulator. Each accumulator section has a control input coupled to a respective output of the control data generator for defining the logic operation of the data accumulator section with respect to the contents of the data shifting unit. The data shifting unit has a plurality of stages each of which is coupled in parallel to the output stage of successive stages of the input data storage unit to which successive digitized data samples of a signal waveform to be processed are coupled. As each respective data sample is coupled to the data shifting unit, the contents of the data shifting unit are incrementally shifted and the resulting digital value is coupled in parallel to each of the sections of the output data accumulator. For each shifted value the parallel arrangement of data accumulator sections controllably combine the contents of the data shifting unit with the current data value stored in each accumulator section in accordance with control codes supplied from the programmable control signal generator.

REFERENCES:
patent: 4328555 (1982-05-01), Nussbaumer
patent: 4547862 (1985-10-01), McIver et al.

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