High speed serializer/deserializer transmit architecture

Details High speed serializer/deserializer transmit architecture High speed serializer/deserializer transmit architecture

2007-11-13

2010-06-29

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

Serial to parallel

C341S101000

Reexamination Certificate

active

07746251

ABSTRACT:
A Serializer/Deserializer apparatus comprises a serializer adapted to take N parallel bits of data and shifts them out serially at N times a clock speed to a transmitter, a transmitter enable block adapted to start the serializer means, and a count block. The serializer comprises flip-flops and muxes, and is adapted to N parallel bits of data and shifts them out serially at N times a clock speed to a transmitter. The transmitter enable block comprises an inverter and flip-flops, and is adapted to start the serializer. The transmitter enable block comprises an inverter, flip-flops, and a NOR gate, and is adapted to create a waveform which programs data loading in the serializer.

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International Search Report—PCT/US07/084596, International Search Authority—European Patent Office—Jun. 5, 2008.
Written Opinion—PCT/US07/084596, International Search Authority—European Patent Office—Jun. 5, 2008.

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