Pulse or digital communications – Receivers
Reexamination Certificate
2008-05-28
2011-11-15
Tran, Khai (Department: 2611)
Pulse or digital communications
Receivers
Reexamination Certificate
active
08059756
ABSTRACT:
A high-speed serial link receiver includes variable offset comparators with centrally controlled offset cancellation. The receiver includes a comparator stage to receive a high-speed differential input signal. Comparator elements of the comparator stage have first and second current sources to provide current to corresponding differential amplifier half-circuits. An offset cancellation controller provides an offset cancellation signal for setting current provided by one of the current sources to at least partially offset an output offset between the differential amplifier half-circuits. A receiver system may be comprised of a plurality of receiver units for receiving a corresponding plurality of channels over high-speed serial links. A state machine may sequentially determine an offset cancellation code for the comparator elements of the receiver units.
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Mahmud Arif
Wei Fangxing
Gorrie Gregory J.
Intel Corporation
Schwegman Lundberg & Woessner, P.A.
Tran Khai
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