High speed serial link for fully duplexed data communication

Details High speed serial link for fully duplexed data communication High speed serial link for fully duplexed data communication

1998-02-03

2000-08-22

Williams, Howard L.

Coded data generation or conversion

Digital code to digital code converters

Parallel to serial

H03M 900

Patent

active

061079464

ABSTRACT:
A system for converting between parallel data and serial data is described. In the system 10, individual bits of the parallel data 12 are latched into individual registers 117. Each register 117 is coupled to a corresponding AND gate 110 which is also connected to receive phased clock signals. The output terminals of the AND gates 110 are connected to an OR gate 115. Using the system, with appropriately phased clocks, the parallel data is converted into serial data.

REFERENCES:
patent: 3982138 (1976-09-01), Luisi et al.
patent: 3986043 (1976-10-01), Buckley, III et al.
patent: 4352031 (1982-09-01), Holbrook et al.
patent: 4754456 (1988-06-01), Yato et al.
patent: 4877974 (1989-10-01), Kawai et al.
patent: 4891808 (1990-01-01), Williams
patent: 4926423 (1990-05-01), Zukowski
patent: 5004938 (1991-04-01), Lee
patent: 5055842 (1991-10-01), Mueller
patent: 5107264 (1992-04-01), Novof
patent: 5128673 (1992-07-01), Tamamura et al.
patent: 5247652 (1993-09-01), Uda
patent: 5263173 (1993-11-01), Gleason
patent: 5399919 (1995-03-01), Mair
patent: 5479112 (1995-12-01), Choi et al.
patent: 5526360 (1996-06-01), Kraft
K. Lam et al., "Simultaneous Bidirectional Signalling for IC Systems", IEEE 1990.
R. Marbot et al., "Integration of Multiple Bidirectional Point-to-Point Serial Links in the Gigabites per Second Range", Bull Serial Link Technology, Hot Interconnects Symposium, 1993, France.
R. Marbot, "Bull's High-Speed Serial Link Development", Bull Serial Link Technology, Oct. 9, 1991.
"G-Taxichips 1.25 Gbits/sec Data Communications Chipset Preliminary Data Sheet", Vitesse Semiconductor Corporation, Camarillo, CA, Jun. 15, 1993.
T. Knight, Jr. et al., "A Self-Terminating Low-Voltage Swing CMOS Output Driver", IEEE Journal of Solid State Circuits, vol. 23, No. 2, Apr. 1988.

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