High speed serial link for fully duplexed data communication

Details High speed serial link for fully duplexed data communication High speed serial link for fully duplexed data communication

1995-12-29

1998-09-01

Chin, Stephen

Pulse or digital communications

Transceivers

Transmission interface between two stations or terminals

370285, H04J 1500

Patent

active

058021035

ABSTRACT:
A system for converting between parallel data and serial data is described. In the system 10, individual bits of the parallel data 12 are latched into individual registers 117. Each register 117 is coupled to a corresponding AND gate 110 which is also connected to receive phased clock signals. The output terminals of the AND gates 110 are connected to an OR gate 115. Using the system, with appropriately phased clocks, the parallel data is converted into serial data.

REFERENCES:
patent: 4162371 (1979-07-01), Belforte
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C. Yen et al., "The HP 2-Gbaud G-Link Chipset", Hewlett-Packard Co.
K. Lam et al., "Simultaneous Bidirectional Signalling for IC Systems", Dept. of Electrical Engineering and Computer Science, MIT, Cambridge, MA.
R. Marbot et al., "Integration of Multiple Bidirectional Point-to-Point Serial Links in the Gigabites per Second Range", Bull Serial Link Technology, Hot Interconnects Symposium, 1993, France.
R. Marbot, "Bull's High-Speed Serial Link Development", Bull Serial Link Technology, Oct. 9, 1991.
"G-Taxichips 1.25 Gbits/sec Data Communications Chipset Preliminary Data Sheet", Vitesse Semiconductor Corporation, Camarillo, CA, Jun. 15, 1993.
T. Knight, Jr. et al., "A Self-Terminating Low-Voltage Swing CMOS Output Driver", IEEE Journal of Solid State Circuits, vol. 23, No. 2, Apr. 1988.

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