High speed serial line transceivers integrated into a cache...

Details High speed serial line transceivers integrated into a cache... High speed serial line transceivers integrated into a cache...

1998-03-09

2001-12-11

Peikari, B. James (Department: 2186)

Electrical computers and digital processing systems: multicomput

Multicomputer data transferring via shared memory

C709S214000, C709S216000, C709S218000, C711S146000, C711S130000, C711S124000, C710S071000

Reexamination Certificate

active

06330591

ABSTRACT:

This invention relates to computer systems in general and, more particularly, to a high speed serial line transceiver integrated into a cache controller component to support coherent memory transactions in a loosely coupled computer network.
DESCRIPTION OF RELATED ART
The concept of maintaining cache coherency in a tightly coupled computer network is generally well known. Tightly coupled generally implies that the computer clusters or computer processors which make up the computer network are housed in a single enclosure. Because the computer clusters or processors are in an extremely close proximity to each other, cache data transfer lines between clusters or processors may be extremely short, to the limits of direct wiring from board to board inside the housing.
This tight, or close, proximity requires tightly coupled computer networks to be designed either as cluster processors housed in the single enclosure, or as VLSI chips. Cache coherency protocols for tightly coupled computer networks may be grouped in various ways, including the classical solution of informing all other caches of all writes, dynamic directory schemes maintaining a directory by filtering out unnecessary overhead, and bus based schemes based on the assumption that all system communications take place on a bus shared by clustered processors.
The principles of tightly coupled processors can be equally applied to processors connected over remote distances outside a singular enclosure. Coherency is still desirable for computer networks that are remotely connected. For ease of integration into legacy systems, this enhanced system should be manufacturable as a single chip solution, preferably in MOS technology on a monolithic silicon substrate, and not necessarily on more expensive GaAs (gallium arsenide) or BIMOS (Bipolar and MOS) technology. The ability to provide cache location information to the entire cluster so that the entire computer system can identify the location of the most recently updated information anywhere in the cluster is desirable. Also desirable is the ability to cache in a single location all transmissions which cross the system bus, to and from the loosely coupled processors, the associated memories and the input/output subsystems.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by an improved transmit unit core that is tightly integrated into an enhanced cluster cache with controller. Broadly speaking, coherent memory transactions in a loosely coupled computer network are supported by sending all cache updates to all computers in the loosely coupled computer network through high speed, low latency and high bandwidth serial lines linking all computers to all other computers.
Additional features of the transmit unit may include the cluster cache controller optionally including a local cache controller and/or as a local bus controller. The local bus controller is operable to couple the cluster cache to an I/O subsystem. The local cache controller preferably couples through a local cache memory management unit (“MMU”) to a local cache memory. Local cache memory preferably caches data and/or instructions, or locations thereof for the entire computer, making the local computer cache available to the entire computer cluster through the transmit unit.
The transmit unit is preferably embodied within a cluster cache, adapted for use in a computer of a loosely-coupled computer system, which also includes, in one embodiment, a timing generator for generating a clock signal for synchronized timing in the transmit unit, control registers for storing native format control data.
Each transfer unit is designed for transmitting and receiving serialized data. The transfer unit includes a receiver and a transmitter. The receiver includes a receive buffer which receives serialized data. Coupled to the receive buffer is a deserializer. The receiver further includes logic coupled to the deserializer which recovers a clocking signal from a deserialized signal, and coverts serialized data into native format data. The logic is henceforth referred to as a data/clock recovery unit. The data/clock recovery unit coupled to the deserializer recovers the native format data and synchronizes the native format data cache controllers that receive and process the native format data. A receive clock generator receives input from the data/clock recovery unit and maintains synchronization of the native format data. The transmitter receives outgoing data in their native formats and transmits the outgoing data in serialized form. Thus the transmitter includes a serializer coupled to a transmit buffer. Further included with the transmitter is a transmit clock generator which synchronizes serialization and transmission of the serialized data before sending the serialized data to the transmit buffer which holds the serialized data before transmission. The transfer unit is preferably a monolithic circuit, which is also preferably a complementary MOS (or complementary MOS) integrated circuit.
The cluster cache system disclosed is based on leading-edge phase-shifted, phase locked loop (“P-S PLL”) technology. Embodied within the cluster cache system is a local cache controller and cache memory responsive to a respective controller. The cache controller sends and receives information (i.e., data and address indicia) to and from at least one transfer unit associated with each cluster cache system. One or more transfer units allow communication between several loosely coupled cluster cache systems, each of which embody a cluster cache controller and a bus interface unit coupled to a system bus. Each transfer unit is a full-duplex transceiver that includes transmitter and receiver functions. Each transfer unit can send and receive data simultaneously since operation of their transmitter and receiver functions are independent from each other and from activity on the system bus linking multiple processing subsystems.


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