Coded data generation or conversion – Digital code to digital code converters – Serial to parallel
Reexamination Certificate
2008-08-22
2010-02-16
Nguyen, Linh V (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
Serial to parallel
C341S101000, C375S242000, C375S244000, C375S354000, C375S358000, C375S376000
Reexamination Certificate
active
07663515
ABSTRACT:
A high-speed serial interface circuit includes a data receiver circuit, a clock signal receiver circuit, a logic circuit block that includes at least a serial/parallel conversion circuit, a free-running clock signal generation circuit, a clock signal detection circuit, and an output mask circuit. The clock signal detection circuit compares a received clock signal from the clock signal receiver circuit with a free-running clock signal from the free-running clock signal generation circuit to detect whether or not clock signals are transferred through differential clock signal lines. When the clock signal detection circuit has detected that the clock signals are not transferred through the differential clock signal lines, the output mask circuit masks an output signal from the logic circuit block so that the output signal is not transmitted to a circuit in the subsequent stage. The present invention can prevent a partial characteristic variation by NBTI by inputting a free-running clock into a logic block, and operating it.
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Oe Kenichi
Yonezawa Takemi
Harness & Dickey & Pierce P.L.C.
Nguyen Linh V
Seiko Epson Corporation
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