High-speed serial interface architecture for a programmable...

Details High-speed serial interface architecture for a programmable... High-speed serial interface architecture for a programmable...

2007-05-29

2008-12-02

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

Serial to parallel

C375S354000

Reexamination Certificate

active

07460040

ABSTRACT:
A high-speed serial interface for a programmable logic device includes a plurality of features to handle the various issues that may arise with data rates over 1 Gbps and particularly over 1.25 Gbps. Those features may include dynamic phase alignment to control clock-data skew, data realignment (e.g., bit slip circuitry) to account for channel-to-channel skew, full-duplex serializer and deserializer, out-of-range frequency support for low frequencies, and a soft-CDR mode.

REFERENCES:
patent: 6269137 (2001-07-01), Colella et al.
patent: 6724328 (2004-04-01), Lui et al.
patent: 7138837 (2006-11-01), Venkata et al.
patent: 7236553 (2007-06-01), Choi et al.
patent: 7340021 (2008-03-01), Churchill et al.

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