High speed serial interface

Details High speed serial interface High speed serial interface

2005-05-17

2005-05-17

Ghayour, Mohammed (Department: 2631)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

C375S316000, C375S354000

Reexamination Certificate

active

06895062

ABSTRACT:
A high speed serial interface system that compensates for phase drift by over sampling received data packets. The system utilizes a transmitter and receiver that operate within the same clock domain to achieve a frequency lock between the two devices. The receiver receives and samples each data packet at n phase intervals, stores and analyzes the samples to determine phase drift, and resynchronizes the receiver clock to compensate for phase drift on an ongoing basis.

REFERENCES:
patent: 4365330 (1982-12-01), Chopping et al.
patent: 5509037 (1996-04-01), Buckner et al.

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