High-speed serial data transceiver and related methods

Details High-speed serial data transceiver and related methods High-speed serial data transceiver and related methods

2006-06-06

2006-06-06

Chin, Stephen (Department: 2634)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

C375S346000, C375S260000, C375S279000, C375S229000, C370S330000, C370S307000, C439S108000, C439S680000

Reexamination Certificate

active

07058150

ABSTRACT:
A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

REFERENCES:
patent: 5396224 (1995-03-01), Dukes et al.
patent: 5485490 (1996-01-01), Leung et al.
patent: 5550546 (1996-08-01), Noneman et al.
patent: 5554945 (1996-09-01), Lee et al.
patent: 5614855 (1997-03-01), Lee et al.
patent: 5650954 (1997-07-01), Minuhin
patent: 5703905 (1997-12-01), Langberg
patent: 5757857 (1998-05-01), Buchwald
patent: 5768268 (1998-06-01), Kline et al.
patent: 5822143 (1998-10-01), Cloke et al.
patent: 5881107 (1999-03-01), Termerinac et al.
patent: 5881108 (1999-03-01), Herzberg et al.
patent: 5945862 (1999-08-01), Donnelly et al.
patent: 5949820 (1999-09-01), Shih et al.
patent: 5966415 (1999-10-01), Bliss et al.
patent: 6002279 (1999-12-01), Evans et al.
patent: 6005445 (1999-12-01), Katakura
patent: 6009534 (1999-12-01), Chiu et al.
patent: 6038269 (2000-03-01), Raghavan
patent: 6122336 (2000-09-01), Anderson
patent: 6134268 (2000-10-01), McCoy
patent: 6329859 (2001-12-01), Wu
patent: 6359486 (2002-03-01), Chen
patent: 6397048 (2002-05-01), Toda
patent: 6404525 (2002-06-01), Shimomura et al.
patent: 6498694 (2002-12-01), Shah
patent: 6509773 (2003-01-01), Buchwald et al.
patent: 6621862 (2003-09-01), Dabell
patent: 6678842 (2004-01-01), Shaffer et al.
patent: 6791388 (2004-09-01), Buchwald et al.
patent: 2002/0012152 (2002-01-01), Agazzi et al.
patent: 2002/0034222 (2002-03-01), Buchwald et al.
patent: 2002/0039395 (2002-04-01), Buchwald et al.
patent: 2002/0044617 (2002-04-01), Buchwald et al.
patent: 2002/0080898 (2002-06-01), Agazzi et al.
patent: 2003/0086515 (2003-05-01), Trans et al.
patent: 2004/0212416 (2004-10-01), Buchwald et al.
patent: 1 006 697 (2000-06-01), None
patent: 1 139 619 (2001-10-01), None
patent: 0 483 439 (1992-05-01), None
patent: 0 515 074 (1992-11-01), None
patent: 0 805 447 (1997-11-01), None
patent: 0 909 035 (1999-04-01), None
patent: WO 01/29991 (2001-04-01), None
patent: WO 01/54317 (2001-07-01), None
patent: WO 01/65788 (2001-09-01), None
patent: WO 01/84702 (2001-11-01), None
patent: WO 01/84724 (2001-11-01), None
patent: WO02/13424 (2002-02-01), None
patent: WO 02/071616 (2002-09-01), None
Yongsam Moon; a 1 Gbps Transceiver with Receiver-End Deskewing Capability using Non-Uniform Tracked Oversampling and a 250-750 MHZ Four-phase DLL; 1999 Symposium on VLSI Circuit Digest of Technical Papers; 47-48.
Buchwald, A. and Martin, K., “Integrated Fiber-Optic Receivers,” Kluwer Academic Publishers, 1994 (entire book submitted).
Sidiropoulos, S. and Horowitz, M., “A Semidigital Dual Delay-Locked Loop,” IEEE Journal of Solid-State Circuits, IEEE, vol. 32, No. 11, Nov. 1997, pp. 1683-1692.
Copy of International Search Report issued Jan. 24, 2002, for Appln. No. PCT/US01/13613, 7 pages.
Copy of International Search Report issued Apr. 11, 2002, for Appln. No. PCT/US01/13637, 2 pages.
Black, Jr., W. and Hodges, D., “Time Interleaved Converter Arrays,”IEEE Journal of Solid-State Circuits, IEEE, vol. SC-15, No. 6, Dec. 1980, pp. 1022-1029.
Conroy, C. et al., “An 8-b 85-MS/s Parallel Pipeline A/D Converter in 1-μm CMOS,”IEEE Journal of Solid-State Circuits, IEEE, vol. 28, No. 4, Apr. 1993, pp. 447-454.
Dally, W. and Poulton, J., “Transmitter Equalization for 4GB/s Signalling,”Proceedings of Hot Interconnects IV, Palo Alto, CA, 1996, 10 pages.
Ellersick, W. et al., “A Serial-Link Transceiver Based on 8GSample/s A/D and D/A Converters in 0.25μm CMOS,”IEEE International Solid-State Circuits Conference, IEEE, 2001, p. 58-59 and 430.
Ellersick, W. et al., “GAD: A 12-GS/s CMOS 4-bit A/D Converter for an Equalized Multi-Level Link,”Symposium on VLSI Circuits Digest of Technical Papers, 1999, pp. 49-52.
Eklund, J-E. and Gustafsson, F., “Digital Offset Compensation of Time-Interleaved ADC Using Random Chopper Sampling,”IEEE International Symposium on Circuits and Systems, IEEE, May 28-31, 2000, pp. III-447 thru III-450.
Fu, D. et al., “A Digital Background Calibration Techique for Time-Interleaved Analog-to Digital Converters,”IEEE Journal of Solid-State Circuits, IEEE, vol. 33, No. 12, Dec. 1998, pp. 1904-1911.
Guizani, M. and Al-Ali, A., “PC-Compatible Optical Data Acquisition Unit,”Instrumentation and Measurement Technology Conference, IEEE, May 10-12, 1994, pp. 1099-1102.
Jenq, Y.-C., “Digital Spectra of Nonuniformly Sampled Signals: A Robust Sampling Time Offset Estimation Algorithm for Ultra High-Speed Waveform Digitizers Using Interleaving”Transactions on Instrumentation and Measurement, IEEE, vol. 39, No. 1, Feb. 1990, pp. 71-75.
Mason, R. and Taylor, J. T., “High-Speed Electro-Optic Analogue to Digital Converters,”IEEE International Symposium in Circuits and Systems, IEEE, 1993, pp. 1081-1084.
Niewczas, P. et al., “Error Analysis of an Optical Current Transducer Operating with Digital Signal Processing System,”IEEE Transactions on Instrumentation and Measurement, IEEE, vol. 49, No. 6, Dec. 2000, pp. 1254-1259.
Petraglia, A. and Mitra, S., “Analysis of Mismatch Effects Among A/D Converters in a Time-Interleaved Waveform Digitizer,”IEEE Transactions on Instrumentation and Measurement, IEEE, vol. 40, No. 5, Oct. 1991, pp. 831-835.
Sauer-Greff, W. et al.,Maximum-Likelihood Sequence Estimation of Nonlinear Channels in High-Speed Optical Fiber Systems, Apr. 6, 2001, Retreived from the Internet at http://www.ftw.at/Dokumente/010406a.pdf, 29 pages.
Williamson, R.C. et al., “Effects of Crosstalk in Demultiplexers for Photoonic Analog-to-Digital Converters,”Journal of Lightwave Technology, IEEE, vol. 19, No. 2, Feb. 2001, pp. 230-236.
Yang, C-K.,Design Techniques for High-Speed Chip-to-Chip Links, Retrieved from the Internet at http://web.doe.carleton.ca/courses/97578/topic5/Tutorial—SerialLink.pdf, 31 pages.
Yang, C-K.et al., “A Serial-Link Transceiver Based on 8-Gsamples/s A/D and D/A Converters in 0.25-μm CMOS,”IEEE Journal of Solid-State Circuits, IEEE, vol. 36, No. 11, Nov. 2001, pp. 1684-1692.
Zuoxi, T., “Implementation of Digital Multibeam Receiver Based on TMS320C80 for Laser Otoacoustic Remote Sensing,”Proceedings of ICSP2000, IEEE, 2000, pp. 2082-2084.
Agazzi, O. and Lenosky, T.,Algorithm to Postprocess Measured Data, IEEE 802.3ae Equalization Ad Hoc Group, Jan. 10, 2001, 11 pages.
Agazzi, O.,A Link Model for Equalized Optical Receivers, IEEE 80233ae Equalization Ad Hoc Group, Mar. 11, 2001, 30 pages.
Agazzi, O. et al.,DSP-Based Equalization for Optical Channels: Feasibility of a VLSI Implementation, IEEE 802.3ae, New Orleans, Sep. 12-14, 2004, 39 pages.
Agazzi, O. et al.,Interim Observations on Multimode Optical Channels, IEEE 802.3ae—Equalization Ad Hoc, Tampa, Nov. 5, 2000, 29 pages.
Agazzi, O. et al.,Measurements of DMD-Challenged Fibers at 3.125 Gb/s, IEEE 802.3ae Equalization Ad Hoc, Jan. 10, 2001, 33 pages.
Agazzi, O. and Lenosky, T., “Measurement of Non-Stationarity of Gb/s Multimode Fiber Links,” Nov. 24, 2000, 5 pages.
Agazzi, O.,10 Gb/s PMD Using PAM-5 Modulation, IEEE, 802.3 Dallas, Jan. 18-20,

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