High-speed serial data signal interface architectures for...

Details High-speed serial data signal interface architectures for... High-speed serial data signal interface architectures for...

2007-03-19

2010-12-28

Liu, Shuwang (Department: 2611)

Pulse or digital communications

Synchronizers

C375S375000, C375S220000, C375S221000, C331S011000, C370S516000, C365S230060

Reexamination Certificate

active

07860203

ABSTRACT:
A programmable logic device integrated circuit (“PLD”) includes high-speed serial interface (“HSSI”) circuitry in addition to programmable logic circuitry. The HSSI circuitry includes multiple channels of nominal data-handling circuitry (typically including clock and data recovery (“CDR”) circuitry), and at least one channel of nominal clock management unit (“CMU”) circuitry (typically including phase-locked loop (“PLL”) circuitry or the like). To increase the flexibility with which the channels can be used, the nominal data-handling channels are equipped to alternatively perform CMU-type functions, and the nominal CMU channel is equipped to alternatively perform data-handling functions.

REFERENCES:
patent: 6144675 (2000-11-01), Wakabayashi et al.
patent: 7167410 (2007-01-01), Boecker et al.

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